From patchwork Tue Feb 13 17:34:45 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugeniy Paltsev X-Patchwork-Id: 873072 X-Patchwork-Delegate: alexey.brodkin@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zgqmH32JDz9s82 for ; Wed, 14 Feb 2018 04:49:18 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id A8114C21FC4; Tue, 13 Feb 2018 17:38:41 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id A0AA5C21FAE; Tue, 13 Feb 2018 17:36:13 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id A5798C21FC1; Tue, 13 Feb 2018 17:35:19 +0000 (UTC) Received: from smtprelay.synopsys.com (smtprelay4.synopsys.com [198.182.47.9]) by lists.denx.de (Postfix) with ESMTPS id 8B4D9C21FCD for ; Tue, 13 Feb 2018 17:35:15 +0000 (UTC) Received: from mailhost.synopsys.com (mailhost2.synopsys.com [10.13.184.66]) by smtprelay.synopsys.com (Postfix) with ESMTP id 3BC8524E033F for ; Tue, 13 Feb 2018 09:35:14 -0800 (PST) Received: from localhost.internal.synopsys.com (unknown [10.121.3.43]) by mailhost.synopsys.com (Postfix) with ESMTP id 120B92C6; Tue, 13 Feb 2018 09:35:12 -0800 (PST) From: Eugeniy Paltsev To: uboot-snps-arc@synopsys.com Date: Tue, 13 Feb 2018 20:34:45 +0300 Message-Id: <20180213173451.6317-13-Eugeniy.Paltsev@synopsys.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20180213173451.6317-1-Eugeniy.Paltsev@synopsys.com> References: <20180213173451.6317-1-Eugeniy.Paltsev@synopsys.com> Cc: u-boot@lists.denx.de, Alexey Brodkin , Eugeniy Paltsev Subject: [U-Boot] [PATCH 12/18] ARC: mode cache global variables to global data struct X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" There is the problem with current implementation if we start u-boot from ROM, as we use global variables before ther initialization, so these variables are overwritten when we copy .data section from ROM. So move these cache global variables into our arch "global data" structure so that we may really start from ROM. Signed-off-by: Eugeniy Paltsev --- arch/arc/include/asm/global_data.h | 6 ++++++ arch/arc/lib/cache.c | 19 +++++++++---------- 2 files changed, 15 insertions(+), 10 deletions(-) diff --git a/arch/arc/include/asm/global_data.h b/arch/arc/include/asm/global_data.h index f0242f1..43e1343 100644 --- a/arch/arc/include/asm/global_data.h +++ b/arch/arc/include/asm/global_data.h @@ -7,9 +7,15 @@ #ifndef __ASM_ARC_GLOBAL_DATA_H #define __ASM_ARC_GLOBAL_DATA_H +#include + #ifndef __ASSEMBLY__ /* Architecture-specific global data */ struct arch_global_data { + int l1_line_sz; +#if defined(CONFIG_ISA_ARCV2) + int slc_line_sz; +#endif }; #endif /* __ASSEMBLY__ */ diff --git a/arch/arc/lib/cache.c b/arch/arc/lib/cache.c index cb90c60..d31606c 100644 --- a/arch/arc/lib/cache.c +++ b/arch/arc/lib/cache.c @@ -13,6 +13,8 @@ #include #include +DECLARE_GLOBAL_DATA_PTR; + /* Bit values in IC_CTRL */ #define IC_CTRL_CACHE_DISABLE BIT(0) @@ -36,11 +38,8 @@ * But .bss section is not relocated and so it will be initilized before * relocation but will be used after being zeroed. */ -int l1_line_sz __section(".data"); - -#define CACHE_LINE_MASK (~(l1_line_sz - 1)) +#define CACHE_LINE_MASK (~(gd->arch.l1_line_sz - 1)) -int slc_line_sz __section(".data"); bool ioc_exists __section(".data") = false; /* To force enable IOC set ioc_enable to 'true' */ @@ -167,7 +166,7 @@ static void __slc_rgn_op(unsigned long paddr, unsigned long sz, const int op) * END needs to be setup before START (latter triggers the operation) * END can't be same as START, so add (l2_line_sz - 1) to sz */ - end = paddr + sz + slc_line_sz - 1; + end = paddr + sz + gd->arch.slc_line_sz - 1; /* * Upper addresses (ARC_AUX_SLC_RGN_END1 and ARC_AUX_SLC_RGN_START1) @@ -218,7 +217,7 @@ static void read_decode_cache_bcr_arcv2(void) if (slc_exists()) { slc_cfg.word = read_aux_reg(ARC_AUX_SLC_CONFIG); - slc_line_sz = (slc_cfg.fields.lsz == 0) ? 128 : 64; + gd->arch.slc_line_sz = (slc_cfg.fields.lsz == 0) ? 128 : 64; } cbcr.word = read_aux_reg(ARC_BCR_CLUSTER); @@ -233,14 +232,14 @@ void read_decode_cache_bcr(void) ibcr.word = read_aux_reg(ARC_BCR_IC_BUILD); if (ibcr.fields.ver) { - l1_line_sz = ic_line_sz = 8 << ibcr.fields.line_len; + gd->arch.l1_line_sz = ic_line_sz = 8 << ibcr.fields.line_len; if (!ic_line_sz) panic("Instruction exists but line length is 0\n"); } dbcr.word = read_aux_reg(ARC_BCR_DC_BUILD); if (dbcr.fields.ver) { - l1_line_sz = dc_line_sz = 16 << dbcr.fields.line_len; + gd->arch.l1_line_sz = dc_line_sz = 16 << dbcr.fields.line_len; if (!dc_line_sz) panic("Data cache exists but line length is 0\n"); } @@ -361,14 +360,14 @@ static inline void __dcache_line_loop(unsigned long paddr, unsigned long sz, sz += paddr & ~CACHE_LINE_MASK; paddr &= CACHE_LINE_MASK; - num_lines = DIV_ROUND_UP(sz, l1_line_sz); + num_lines = DIV_ROUND_UP(sz, gd->arch.l1_line_sz); while (num_lines-- > 0) { #if (CONFIG_ARC_MMU_VER == 3) write_aux_reg(ARC_AUX_DC_PTAG, paddr); #endif write_aux_reg(aux_cmd, paddr); - paddr += l1_line_sz; + paddr += gd->arch.l1_line_sz; } }