From patchwork Fri Feb 9 03:34:51 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenyou Yang X-Patchwork-Id: 871197 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zd19r60YQz9rxj for ; Fri, 9 Feb 2018 14:43:12 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 8EAB0C21D6A; Fri, 9 Feb 2018 03:42:20 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 43ED3C21EFD; Fri, 9 Feb 2018 03:42:16 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id E480AC21E45; Fri, 9 Feb 2018 03:42:02 +0000 (UTC) Received: from DVREDG01.corp.atmel.com (f5out.microchip.com [198.175.253.81]) by lists.denx.de (Postfix) with ESMTPS id 5A896C21DE8 for ; Fri, 9 Feb 2018 03:41:58 +0000 (UTC) Received: from apsmtp01.atmel.com (10.168.254.31) by DVREDG01.corp.atmel.com (10.10.204.148) with Microsoft SMTP Server (TLS) id 14.3.235.1; Thu, 8 Feb 2018 20:42:12 -0700 Received: from shaarm01.corp.atmel.com (10.168.254.13) by apsmtp01.atmel.com (10.168.254.31) with Microsoft SMTP Server id 14.3.235.1; Fri, 9 Feb 2018 11:50:45 +0800 From: Wenyou Yang To: U-Boot Mailing List Date: Fri, 9 Feb 2018 11:34:51 +0800 Message-ID: <20180209033452.15448-3-wenyou.yang@microchip.com> X-Mailer: git-send-email 2.16.0.rc1 In-Reply-To: <20180209033452.15448-1-wenyou.yang@microchip.com> References: <20180209033452.15448-1-wenyou.yang@microchip.com> MIME-Version: 1.0 Cc: Tom Rini , Nicolas Ferre , Wenyou Yang Subject: [U-Boot] [PATCH 2/3] clk: at91: add PLLADIV driver X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" As said in the SAMA5D2 datasheet, the PLLA clock must be divided by 2 by writing the PLLADIV2 bit in PMC_MCKR, if the ratio between PCK and MCK is 3 (MDIV = 3). This is the purpose of the driver. Signed-off-by: Wenyou Yang --- drivers/clk/at91/Makefile | 2 +- drivers/clk/at91/clk-plladiv.c | 88 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 89 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/at91/clk-plladiv.c diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile index 8cac3f9e18..8c197ff949 100644 --- a/drivers/clk/at91/Makefile +++ b/drivers/clk/at91/Makefile @@ -3,7 +3,7 @@ # obj-y += pmc.o sckc.o -obj-y += clk-slow.o clk-main.o clk-plla.o clk-master.o +obj-y += clk-slow.o clk-main.o clk-plla.o clk-plladiv.o clk-master.o obj-y += clk-system.o clk-peripheral.o obj-$(CONFIG_AT91_UTMI) += clk-utmi.o diff --git a/drivers/clk/at91/clk-plladiv.c b/drivers/clk/at91/clk-plladiv.c new file mode 100644 index 0000000000..0599d2893b --- /dev/null +++ b/drivers/clk/at91/clk-plladiv.c @@ -0,0 +1,88 @@ +/* + * Copyright (C) 2018 Microhip / Atmel Corporation + * Wenyou.Yang + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include "pmc.h" + +DECLARE_GLOBAL_DATA_PTR; + +static int at91_plladiv_clk_enable(struct clk *clk) +{ + return 0; +} + +static ulong at91_plladiv_clk_get_rate(struct clk *clk) +{ + struct pmc_platdata *plat = dev_get_platdata(clk->dev); + struct at91_pmc *pmc = plat->reg_base; + struct clk source; + ulong clk_rate; + int ret; + + ret = clk_get_by_index(clk->dev, 0, &source); + if (ret) + return -EINVAL; + + clk_rate = clk_get_rate(&source); + if (readl(&pmc->mckr) & AT91_PMC_MCKR_PLLADIV_2) + clk_rate /= 2; + + return clk_rate; +} + +static ulong at91_plladiv_clk_set_rate(struct clk *clk, ulong rate) +{ + struct pmc_platdata *plat = dev_get_platdata(clk->dev); + struct at91_pmc *pmc = plat->reg_base; + struct clk source; + ulong parent_rate; + int ret; + + ret = clk_get_by_index(clk->dev, 0, &source); + if (ret) + return -EINVAL; + + parent_rate = clk_get_rate(&source); + if ((parent_rate != rate) && ((parent_rate) / 2 != rate)) + return -EINVAL; + + if (parent_rate != rate) { + writel((readl(&pmc->mckr) | AT91_PMC_MCKR_PLLADIV_2), + &pmc->mckr); + } + + return 0; +} + +static struct clk_ops at91_plladiv_clk_ops = { + .enable = at91_plladiv_clk_enable, + .get_rate = at91_plladiv_clk_get_rate, + .set_rate = at91_plladiv_clk_set_rate, +}; + +static int at91_plladiv_clk_probe(struct udevice *dev) +{ + return at91_pmc_core_probe(dev); +} + +static const struct udevice_id at91_plladiv_clk_match[] = { + { .compatible = "atmel,at91sam9x5-clk-plldiv" }, + {} +}; + +U_BOOT_DRIVER(at91_plladiv_clk) = { + .name = "at91-plladiv-clk", + .id = UCLASS_CLK, + .of_match = at91_plladiv_clk_match, + .probe = at91_plladiv_clk_probe, + .platdata_auto_alloc_size = sizeof(struct pmc_platdata), + .ops = &at91_plladiv_clk_ops, +};