From patchwork Wed Jan 24 22:17:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 865506 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="XFKBGvK2"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zRfnV3dmsz9s1h for ; Thu, 25 Jan 2018 09:23:10 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 21A0FC21FBE; Wed, 24 Jan 2018 22:22:49 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 6BE2FC21F8E; Wed, 24 Jan 2018 22:19:14 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id E600EC21F74; Wed, 24 Jan 2018 22:18:08 +0000 (UTC) Received: from mail-wr0-f196.google.com (mail-wr0-f196.google.com [209.85.128.196]) by lists.denx.de (Postfix) with ESMTPS id 37C75C21F90 for ; Wed, 24 Jan 2018 22:18:01 +0000 (UTC) Received: by mail-wr0-f196.google.com with SMTP id v15so5627877wrb.8 for ; Wed, 24 Jan 2018 14:18:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=j29xk4ieZnG8CCk9dg2+geio1YnV2QQu4/TH1eKYKvY=; b=XFKBGvK2pXKLnPy0FgZh3ADS6anF3sXYLNh/ScDYtaqhaiFguVs37Az+6RNolfKDoA TQbK6RDq/LfHTJGw0gkfU/69JxWC6jk3NhTtm1mU/Sn25KIc6/Hie0Hii69RFUD8h7wx /1/oZW2pfiqcYcqApF0bcCDvtpBWAYwSwb5stgbsOmC4uuJGZth4iqy2yEgikfCB5zWQ yKPWEojOboOCCh0a7O6iyQH192P68yRHTaAGbzZe5bh3/zArbaptLfJG4+YAENBHJq0u oNq0+vUSduVT85OiIqxOF+M9HAv60Q5uAdKg5f9qQUXRur2zSni9D/MCBtDEqj6Dz/I2 yo4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=j29xk4ieZnG8CCk9dg2+geio1YnV2QQu4/TH1eKYKvY=; b=I2ve27gRXX2TgTmCG/z0hy2bNWPezvrnBTkVdloqFdoJhwfrNW/GkyM7sw8RvM7I4s McppV9zAuXw9ZgtCfSlCDccE4sa5m5xugHX4gcj0MWbSMCekD4OJX+ggdQfJtcp5qbtH FUXa0H04AWbbscWFgSXefX/O5VZj+31RbuVbePRozroouuMZI0Z+QyfkkWfeCCxd5/ND NOSU7XlMAgHSe5FTtijP/MVPQTt3+aAw9r6wrBfY6pU2fXz0wwcKYE7sZoaeRhL6vAdX +phYO4/yA5hk05h02qVNOezv/X9A08+lu6ydNSFMyX4hSPDnd4RBW69IoWtOURHbhaBv Ja5A== X-Gm-Message-State: AKwxytcVt+oLrNJBPpUfba081a82EE6fOEdX8HUU1lpj7CIZ/SgYEbFR fzu4/EEochEwqVjugMM0zwLghop9 X-Google-Smtp-Source: AH8x227bzuV9k4el6ZNf0EufIL4gfP87L3HDR4ZvV1ba0pDT+rn7q59u6iJUwG2pZwj9p+rSmiyGKw== X-Received: by 10.223.157.205 with SMTP id q13mr7031665wre.205.1516832280453; Wed, 24 Jan 2018 14:18:00 -0800 (PST) Received: from kurokawa.lan (ip-86-49-107-50.net.upcbroadband.cz. [86.49.107.50]) by smtp.gmail.com with ESMTPSA id l41sm6532348wrl.1.2018.01.24.14.17.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 24 Jan 2018 14:17:59 -0800 (PST) From: Marek Vasut X-Google-Original-From: Marek Vasut To: u-boot@lists.denx.de Date: Wed, 24 Jan 2018 23:17:40 +0100 Message-Id: <20180124221750.14369-3-marek.vasut+renesas@gmail.com> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180124221750.14369-1-marek.vasut+renesas@gmail.com> References: <20180124221750.14369-1-marek.vasut+renesas@gmail.com> Cc: Marek Vasut Subject: [U-Boot] [PATCH 03/13] clk: renesas: Make PLL configurations per-SoC X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Not all SoCs have the same PLL configuration options, so make those PLL configuraion tables per-SoC. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- drivers/clk/renesas/clk-rcar-gen3.c | 53 ++----------------------------- drivers/clk/renesas/r8a7795-cpg-mssr.c | 56 +++++++++++++++++++++++++++++++++ drivers/clk/renesas/r8a7796-cpg-mssr.c | 56 +++++++++++++++++++++++++++++++++ drivers/clk/renesas/r8a77970-cpg-mssr.c | 39 +++++++++++++++++++++++ drivers/clk/renesas/r8a77995-cpg-mssr.c | 24 ++++++++++++++ drivers/clk/renesas/renesas-cpg-mssr.h | 1 + 6 files changed, 178 insertions(+), 51 deletions(-) diff --git a/drivers/clk/renesas/clk-rcar-gen3.c b/drivers/clk/renesas/clk-rcar-gen3.c index 647e8e1d9c..76c6de2ab2 100644 --- a/drivers/clk/renesas/clk-rcar-gen3.c +++ b/drivers/clk/renesas/clk-rcar-gen3.c @@ -74,56 +74,6 @@ static const u16 smstpcr[] = { /* Software Reset Clearing Register offsets */ #define SRSTCLR(i) (0x940 + (i) * 4) -/* - * CPG Clock Data - */ - -/* - * MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4 - * 14 13 19 17 (MHz) - *------------------------------------------------------------------- - * 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144 - * 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144 - * 0 0 1 0 Prohibited setting - * 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144 - * 0 1 0 0 20 x 1 x150 x160 x120 x160 x120 - * 0 1 0 1 20 x 1 x150 x160 x120 x106 x120 - * 0 1 1 0 Prohibited setting - * 0 1 1 1 20 x 1 x150 x160 x120 x160 x120 - * 1 0 0 0 25 x 1 x120 x128 x96 x128 x96 - * 1 0 0 1 25 x 1 x120 x128 x96 x84 x96 - * 1 0 1 0 Prohibited setting - * 1 0 1 1 25 x 1 x120 x128 x96 x128 x96 - * 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144 - * 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144 - * 1 1 1 0 Prohibited setting - * 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144 - */ -#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \ - (((md) & BIT(13)) >> 11) | \ - (((md) & BIT(19)) >> 18) | \ - (((md) & BIT(17)) >> 17)) - -static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] = { - /* EXTAL div PLL1 mult PLL3 mult */ - { 1, 192, 192, }, - { 1, 192, 128, }, - { 0, /* Prohibited setting */ }, - { 1, 192, 192, }, - { 1, 160, 160, }, - { 1, 160, 106, }, - { 0, /* Prohibited setting */ }, - { 1, 160, 160, }, - { 1, 128, 128, }, - { 1, 128, 84, }, - { 0, /* Prohibited setting */ }, - { 1, 128, 128, }, - { 2, 192, 192, }, - { 2, 192, 128, }, - { 0, /* Prohibited setting */ }, - { 2, 192, 192, }, -}; - /* * SDn Clock */ @@ -520,7 +470,8 @@ int gen3_clk_probe(struct udevice *dev) cpg_mode = readl(rst_base + CPG_RST_MODEMR); - priv->cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; + priv->cpg_pll_config = + (struct rcar_gen3_cpg_pll_config *)info->get_pll_config(cpg_mode); if (!priv->cpg_pll_config->extal_div) return -EINVAL; diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c index ecbb9b31de..144d9becd9 100644 --- a/drivers/clk/renesas/r8a7795-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c @@ -264,6 +264,56 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] = { DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)), }; +/* + * CPG Clock Data + */ + +/* + * MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4 + * 14 13 19 17 (MHz) + *------------------------------------------------------------------- + * 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144 + * 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144 + * 0 0 1 0 Prohibited setting + * 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144 + * 0 1 0 0 20 x 1 x150 x160 x120 x160 x120 + * 0 1 0 1 20 x 1 x150 x160 x120 x106 x120 + * 0 1 1 0 Prohibited setting + * 0 1 1 1 20 x 1 x150 x160 x120 x160 x120 + * 1 0 0 0 25 x 1 x120 x128 x96 x128 x96 + * 1 0 0 1 25 x 1 x120 x128 x96 x84 x96 + * 1 0 1 0 Prohibited setting + * 1 0 1 1 25 x 1 x120 x128 x96 x128 x96 + * 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144 + * 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144 + * 1 1 1 0 Prohibited setting + * 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144 + */ +#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \ + (((md) & BIT(13)) >> 11) | \ + (((md) & BIT(19)) >> 18) | \ + (((md) & BIT(17)) >> 17)) + +static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] = { + /* EXTAL div PLL1 mult/div PLL3 mult/div */ + { 1, 192, 1, 192, 1, }, + { 1, 192, 1, 128, 1, }, + { 0, /* Prohibited setting */ }, + { 1, 192, 1, 192, 1, }, + { 1, 160, 1, 160, 1, }, + { 1, 160, 1, 106, 1, }, + { 0, /* Prohibited setting */ }, + { 1, 160, 1, 160, 1, }, + { 1, 128, 1, 128, 1, }, + { 1, 128, 1, 84, 1, }, + { 0, /* Prohibited setting */ }, + { 1, 128, 1, 128, 1, }, + { 2, 192, 1, 192, 1, }, + { 2, 192, 1, 128, 1, }, + { 0, /* Prohibited setting */ }, + { 2, 192, 1, 192, 1, }, +}; + static const struct mstp_stop_table r8a7795_mstp_table[] = { { 0x00640800, 0x0 }, { 0xF3EE9390, 0x0 }, { 0x340FAFDC, 0x2040 }, { 0xD80C7CDF, 0x400 }, @@ -273,6 +323,11 @@ static const struct mstp_stop_table r8a7795_mstp_table[] = { { 0xFFFEFFE0, 0x0 }, { 0x00000000, 0x0 }, }; +static const void *r8a7795_get_pll_config(const u32 cpg_mode) +{ + return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; +} + static const struct cpg_mssr_info r8a7795_cpg_mssr_info = { .core_clk = r8a7795_core_clks, .core_clk_size = ARRAY_SIZE(r8a7795_core_clks), @@ -285,6 +340,7 @@ static const struct cpg_mssr_info r8a7795_cpg_mssr_info = { .mod_clk_base = MOD_CLK_BASE, .clk_extal_id = CLK_EXTAL, .clk_extalr_id = CLK_EXTALR, + .get_pll_config = r8a7795_get_pll_config, }; static const struct udevice_id r8a7795_clk_ids[] = { diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c index 6da3b14166..016ab3dc28 100644 --- a/drivers/clk/renesas/r8a7796-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c @@ -237,6 +237,56 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] = { DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)), }; +/* + * CPG Clock Data + */ + +/* + * MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4 + * 14 13 19 17 (MHz) + *------------------------------------------------------------------- + * 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144 + * 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144 + * 0 0 1 0 Prohibited setting + * 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144 + * 0 1 0 0 20 x 1 x150 x160 x120 x160 x120 + * 0 1 0 1 20 x 1 x150 x160 x120 x106 x120 + * 0 1 1 0 Prohibited setting + * 0 1 1 1 20 x 1 x150 x160 x120 x160 x120 + * 1 0 0 0 25 x 1 x120 x128 x96 x128 x96 + * 1 0 0 1 25 x 1 x120 x128 x96 x84 x96 + * 1 0 1 0 Prohibited setting + * 1 0 1 1 25 x 1 x120 x128 x96 x128 x96 + * 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144 + * 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144 + * 1 1 1 0 Prohibited setting + * 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144 + */ +#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \ + (((md) & BIT(13)) >> 11) | \ + (((md) & BIT(19)) >> 18) | \ + (((md) & BIT(17)) >> 17)) + +static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] = { + /* EXTAL div PLL1 mult/div PLL3 mult/div */ + { 1, 192, 1, 192, 1, }, + { 1, 192, 1, 128, 1, }, + { 0, /* Prohibited setting */ }, + { 1, 192, 1, 192, 1, }, + { 1, 160, 1, 160, 1, }, + { 1, 160, 1, 106, 1, }, + { 0, /* Prohibited setting */ }, + { 1, 160, 1, 160, 1, }, + { 1, 128, 1, 128, 1, }, + { 1, 128, 1, 84, 1, }, + { 0, /* Prohibited setting */ }, + { 1, 128, 1, 128, 1, }, + { 2, 192, 1, 192, 1, }, + { 2, 192, 1, 128, 1, }, + { 0, /* Prohibited setting */ }, + { 2, 192, 1, 192, 1, }, +}; + static const struct mstp_stop_table r8a7796_mstp_table[] = { { 0x00200000, 0x0 }, { 0xFFFFFFFF, 0x0 }, { 0x340E2FDC, 0x2040 }, { 0xFFFFFFDF, 0x400 }, @@ -246,6 +296,11 @@ static const struct mstp_stop_table r8a7796_mstp_table[] = { { 0xFFFEFFE0, 0x0 }, { 0x000000B7, 0x0 }, }; +static const void *r8a7796_get_pll_config(const u32 cpg_mode) +{ + return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; +} + static const struct cpg_mssr_info r8a7796_cpg_mssr_info = { .core_clk = r8a7796_core_clks, .core_clk_size = ARRAY_SIZE(r8a7796_core_clks), @@ -258,6 +313,7 @@ static const struct cpg_mssr_info r8a7796_cpg_mssr_info = { .mod_clk_base = MOD_CLK_BASE, .clk_extal_id = CLK_EXTAL, .clk_extalr_id = CLK_EXTALR, + .get_pll_config = r8a7796_get_pll_config, }; static const struct udevice_id r8a7796_clk_ids[] = { diff --git a/drivers/clk/renesas/r8a77970-cpg-mssr.c b/drivers/clk/renesas/r8a77970-cpg-mssr.c index fe36b11f7e..782ea25262 100644 --- a/drivers/clk/renesas/r8a77970-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77970-cpg-mssr.c @@ -145,6 +145,39 @@ static const struct mssr_mod_clk r8a77970_mod_clks[] = { DEF_MOD("i2c0", 931, R8A77970_CLK_S2D2), }; +/* + * CPG Clock Data + */ + +/* + * MD EXTAL PLL0 PLL1 PLL3 + * 14 13 19 (MHz) + *------------------------------------------------- + * 0 0 0 16.66 x 1 x192 x192 x96 + * 0 0 1 16.66 x 1 x192 x192 x80 + * 0 1 0 20 x 1 x160 x160 x80 + * 0 1 1 20 x 1 x160 x160 x66 + * 1 0 0 27 / 2 x236 x236 x118 + * 1 0 1 27 / 2 x236 x236 x98 + * 1 1 0 33.33 / 2 x192 x192 x96 + * 1 1 1 33.33 / 2 x192 x192 x80 + */ +#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \ + (((md) & BIT(13)) >> 12) | \ + (((md) & BIT(19)) >> 19)) + +static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[8] = { + /* EXTAL div PLL1 mult/div PLL3 mult/div */ + { 1, 192, 1, 96, 1, }, + { 1, 192, 1, 80, 1, }, + { 1, 160, 1, 80, 1, }, + { 1, 160, 1, 66, 1, }, + { 2, 236, 1, 118, 1, }, + { 2, 236, 1, 98, 1, }, + { 2, 192, 1, 96, 1, }, + { 2, 192, 1, 80, 1, }, +}; + static const struct mstp_stop_table r8a77970_mstp_table[] = { { 0x00230000, 0x0 }, { 0xFFFFFFFF, 0x0 }, { 0x14062FD8, 0x2040 }, { 0xFFFFFFDF, 0x400 }, @@ -154,6 +187,11 @@ static const struct mstp_stop_table r8a77970_mstp_table[] = { { 0xFFFEFFE0, 0x0 }, { 0x000000B7, 0x0 }, }; +static const void *r8a77970_get_pll_config(const u32 cpg_mode) +{ + return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; +} + static const struct cpg_mssr_info r8a77970_cpg_mssr_info = { .core_clk = r8a77970_core_clks, .core_clk_size = ARRAY_SIZE(r8a77970_core_clks), @@ -166,6 +204,7 @@ static const struct cpg_mssr_info r8a77970_cpg_mssr_info = { .mod_clk_base = MOD_CLK_BASE, .clk_extal_id = CLK_EXTAL, .clk_extalr_id = CLK_EXTALR, + .get_pll_config = r8a77970_get_pll_config, }; static const struct udevice_id r8a77970_clk_ids[] = { diff --git a/drivers/clk/renesas/r8a77995-cpg-mssr.c b/drivers/clk/renesas/r8a77995-cpg-mssr.c index c754c1356f..2e07cb2768 100644 --- a/drivers/clk/renesas/r8a77995-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77995-cpg-mssr.c @@ -169,6 +169,24 @@ static const struct mssr_mod_clk r8a77995_mod_clks[] = { DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)), }; +/* + * CPG Clock Data + */ + +/* + * MD19 EXTAL (MHz) PLL0 PLL1 PLL3 + *-------------------------------------------------------------------- + * 0 48 x 1 x250/4 x100/3 x100/3 + * 1 48 x 1 x250/4 x100/3 x116/6 + */ +#define CPG_PLL_CONFIG_INDEX(md) (((md) & BIT(19)) >> 19) + +static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[2] __initconst = { + /* EXTAL div PLL1 mult/div PLL3 mult/div */ + { 1, 100, 3, 100, 3, }, + { 1, 100, 3, 116, 6, }, +}; + static const struct mstp_stop_table r8a77995_mstp_table[] = { { 0x00200000, 0x0 }, { 0xFFFFFFFF, 0x0 }, { 0x340E2FDC, 0x2040 }, { 0xFFFFFFDF, 0x400 }, @@ -178,6 +196,11 @@ static const struct mstp_stop_table r8a77995_mstp_table[] = { { 0xFFFEFFE0, 0x0 }, { 0x000000B7, 0x0 }, }; +static const void *r8a77995_get_pll_config(const u32 cpg_mode) +{ + return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; +} + static const struct cpg_mssr_info r8a77995_cpg_mssr_info = { .core_clk = r8a77995_core_clks, .core_clk_size = ARRAY_SIZE(r8a77995_core_clks), @@ -189,6 +212,7 @@ static const struct cpg_mssr_info r8a77995_cpg_mssr_info = { .mod_clk_base = MOD_CLK_BASE, .clk_extal_id = CLK_EXTAL, .clk_extalr_id = ~0, + .get_pll_config = r8a77995_get_pll_config, }; static const struct udevice_id r8a77995_clk_ids[] = { diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h b/drivers/clk/renesas/renesas-cpg-mssr.h index 2303baa1fd..eee8b8f5cb 100644 --- a/drivers/clk/renesas/renesas-cpg-mssr.h +++ b/drivers/clk/renesas/renesas-cpg-mssr.h @@ -26,6 +26,7 @@ struct cpg_mssr_info { unsigned int mod_clk_base; unsigned int clk_extal_id; unsigned int clk_extalr_id; + const void *(*get_pll_config)(const u32 cpg_mode); }; struct gen3_clk_priv {