| Message ID | 20180124004454.5759-8-miquel.raynal@free-electrons.com |
|---|---|
| State | Changes Requested |
| Delegated to: | Jagannadha Sutradharudu Teki |
| Headers | show |
| Series | Bring NAND support to Nintendo NES Classic | expand |
Hi, On Wed, Jan 24, 2018 at 01:44:53AM +0100, Miquel Raynal wrote: > Add the NAND controller node, as well as the definition of the missing > pins and clock. > > Signed-off-by: Miquel Raynal <miquel.raynal@free-electrons.com> > --- > arch/arm/dts/sun8i-a23-a33.dtsi | 31 +++++++++++++++++++++++++++++++ > arch/arm/dts/sun8i-a33.dtsi | 8 ++++++++ > 2 files changed, 39 insertions(+) > > diff --git a/arch/arm/dts/sun8i-a23-a33.dtsi b/arch/arm/dts/sun8i-a23-a33.dtsi > index f97c38f097..fe6ea82cb3 100644 > --- a/arch/arm/dts/sun8i-a23-a33.dtsi > +++ b/arch/arm/dts/sun8i-a23-a33.dtsi > @@ -325,6 +325,19 @@ > #size-cells = <0>; > }; > > + nfc: nand@01c03000 { > + compatible = "allwinner,sun4i-a10-nand"; > + reg = <0x01c03000 0x1000>; > + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ahb1_gates 25>, <&nand_clk>; > + clock-names = "ahb", "mod"; > + resets = <&ahb1_rst 10>; > + reset-names = "ahb"; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + That node is already there so that patch shouldn't be needed.
diff --git a/arch/arm/dts/sun8i-a23-a33.dtsi b/arch/arm/dts/sun8i-a23-a33.dtsi index f97c38f097..fe6ea82cb3 100644 --- a/arch/arm/dts/sun8i-a23-a33.dtsi +++ b/arch/arm/dts/sun8i-a23-a33.dtsi @@ -325,6 +325,19 @@ #size-cells = <0>; }; + nfc: nand@01c03000 { + compatible = "allwinner,sun4i-a10-nand"; + reg = <0x01c03000 0x1000>; + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ahb1_gates 25>, <&nand_clk>; + clock-names = "ahb", "mod"; + resets = <&ahb1_rst 10>; + reset-names = "ahb"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + ehci0: usb@01c1a000 { compatible = "allwinner,sun8i-a23-ehci", "generic-ehci"; reg = <0x01c1a000 0x100>; @@ -364,6 +377,24 @@ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; }; + nand_pins_a: nand-base0@0 { + allwinner,pins = "PC0", "PC1", "PC2", + "PC5", "PC8", "PC9", "PC10", + "PC11", "PC12", "PC13", "PC14", + "PC15"; + allwinner,function = "nand0"; + }; + + nand_cs0_pins_a: nand-cs@0 { + allwinner,pins = "PC4"; + allwinner,function = "nand0"; + }; + + nand_rb0_pins_a: nand-rb@0 { + allwinner,pins = "PC6"; + allwinner,function = "nand0"; + }; + mmc0_pins_a: mmc0@0 { allwinner,pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; diff --git a/arch/arm/dts/sun8i-a33.dtsi b/arch/arm/dts/sun8i-a33.dtsi index 001d8402ca..2ef817a679 100644 --- a/arch/arm/dts/sun8i-a33.dtsi +++ b/arch/arm/dts/sun8i-a33.dtsi @@ -99,6 +99,14 @@ "ahb1_sat"; }; + nand_clk: clk@01c20080 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c20080 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "nand"; + }; + ss_clk: clk@01c2009c { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-mod0-clk";
Add the NAND controller node, as well as the definition of the missing pins and clock. Signed-off-by: Miquel Raynal <miquel.raynal@free-electrons.com> --- arch/arm/dts/sun8i-a23-a33.dtsi | 31 +++++++++++++++++++++++++++++++ arch/arm/dts/sun8i-a33.dtsi | 8 ++++++++ 2 files changed, 39 insertions(+)