From patchwork Fri Dec 29 06:17:47 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lokesh Vutla X-Patchwork-Id: 853621 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="oa4aRFOb"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3z7GjT5frcz9s1h for ; Fri, 29 Dec 2017 17:22:53 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 602BCC21DD0; Fri, 29 Dec 2017 06:19:23 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id E403EC21DDE; Fri, 29 Dec 2017 06:18:59 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 8579AC21DCE; Fri, 29 Dec 2017 06:18:42 +0000 (UTC) Received: from lelnx194.ext.ti.com (lelnx194.ext.ti.com [198.47.27.80]) by lists.denx.de (Postfix) with ESMTPS id 267E2C21DE7 for ; Fri, 29 Dec 2017 06:18:42 +0000 (UTC) Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx194.ext.ti.com (8.15.1/8.15.1) with ESMTP id vBT6IeIO024113; Fri, 29 Dec 2017 00:18:40 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1514528320; bh=/t5PbQER0CdMr8comnrXhWlZOYmEnZNvevTIX/gY2r4=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=oa4aRFObIUp4k1HZHfMI0RB6SJomazmQAToWDMQ5tlmXg25n0ExshdQdXgotMbgdp tb6U1FGlXnZxW9xmsBb3Yw/qdKrIQKu1D7W9wpfRDi7BrU6esk9olasAPTJMt/+yMm 58vjIe43onIm1qmwgXK1WLU6Gs93iZKY9qDIKwBc= Received: from DFLE107.ent.ti.com (dfle107.ent.ti.com [10.64.6.28]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id vBT6IeuR025508; Fri, 29 Dec 2017 00:18:40 -0600 Received: from DFLE111.ent.ti.com (10.64.6.32) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.35; Fri, 29 Dec 2017 00:18:39 -0600 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1261.35 via Frontend Transport; Fri, 29 Dec 2017 00:18:39 -0600 Received: from uda0131933.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id vBT6IXZu005132; Fri, 29 Dec 2017 00:18:38 -0600 From: Lokesh Vutla To: Tom Rini , Date: Fri, 29 Dec 2017 11:47:47 +0530 Message-ID: <20171229061758.17983-3-lokeshvutla@ti.com> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20171229061758.17983-1-lokeshvutla@ti.com> References: <20171229061758.17983-1-lokeshvutla@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: Tero Kristo Subject: [U-Boot] [PATCH v2 02/13] arm: emif-common: Add ecc specific emif registers X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This is a slight difference in emif_ddr_phy_status register offsets for DRA7xx EMIF and older versions. And ecc registers are available only in DRA7xx EMIC. Add support for this difference and ecc registers. Signed-off-by: Lokesh Vutla --- arch/arm/include/asm/emif.h | 17 ++++++++++++++++- arch/arm/mach-omap2/emif-common.c | 6 +++--- 2 files changed, 19 insertions(+), 4 deletions(-) diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h index 9a46340deb..a661ba9032 100644 --- a/arch/arm/include/asm/emif.h +++ b/arch/arm/include/asm/emif.h @@ -664,12 +664,27 @@ struct emif_reg_struct { u32 emif_prio_class_serv_map; u32 emif_connect_id_serv_1_map; u32 emif_connect_id_serv_2_map; - u32 padding8[5]; + u32 padding8; + u32 emif_ecc_ctrl_reg; + u32 emif_ecc_address_range_1; + u32 emif_ecc_address_range_2; + u32 padding8_1; u32 emif_rd_wr_exec_thresh; u32 emif_cos_config; +#if defined(CONFIG_DRA7XX) || defined(CONFIG_ARCH_KEYSTONE) + u32 padding9[2]; + u32 emif_1b_ecc_err_cnt; + u32 emif_1b_ecc_err_thrush; + u32 emif_1b_ecc_err_dist_1; + u32 emif_1b_ecc_err_addr_log; + u32 emif_2b_ecc_err_addr_log; + u32 emif_ddr_phy_status[28]; + u32 padding10[19]; +#else u32 padding9[6]; u32 emif_ddr_phy_status[28]; u32 padding10[20]; +#endif u32 emif_ddr_ext_phy_ctrl_1; u32 emif_ddr_ext_phy_ctrl_1_shdw; u32 emif_ddr_ext_phy_ctrl_2; diff --git a/arch/arm/mach-omap2/emif-common.c b/arch/arm/mach-omap2/emif-common.c index def7fe0f0a..2b03dbecf4 100644 --- a/arch/arm/mach-omap2/emif-common.c +++ b/arch/arm/mach-omap2/emif-common.c @@ -255,7 +255,7 @@ static void update_hwleveling_output(u32 base, const struct emif_regs *regs) u32 *emif_ext_phy_ctrl_reg, *emif_phy_status; u32 reg, i, phy; - emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[7]; + emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[6]; phy = readl(&emif->emif_ddr_phy_ctrl_1); /* Update PHY_REG_RDDQS_RATIO */ @@ -269,7 +269,7 @@ static void update_hwleveling_output(u32 base, const struct emif_regs *regs) /* Update PHY_REG_FIFO_WE_SLAVE_RATIO */ emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_2; - emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[12]; + emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[11]; if (!(phy & EMIF_DDR_PHY_CTRL_1_RDLVLGATE_MASK_MASK)) for (i = 0; i < PHY_FIFO_WE_SLAVE_RATIO_REGS; i++) { reg = readl(emif_phy_status++); @@ -279,7 +279,7 @@ static void update_hwleveling_output(u32 base, const struct emif_regs *regs) /* Update PHY_REG_WR_DQ/DQS_SLAVE_RATIO */ emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_12; - emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[17]; + emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[16]; if (!(phy & EMIF_DDR_PHY_CTRL_1_WRLVL_MASK_MASK)) for (i = 0; i < PHY_REG_WR_DQ_SLAVE_RATIO_REGS; i++) { reg = readl(emif_phy_status++);