From patchwork Fri Sep 22 07:26:33 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen-Yu Tsai X-Patchwork-Id: 817349 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3xz4sK5bs3z9sNc for ; Fri, 22 Sep 2017 17:31:01 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 75E51C21E0E; Fri, 22 Sep 2017 07:28:50 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id A50AFC21FBB; Fri, 22 Sep 2017 07:27:04 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id C4F59C21F4B; Fri, 22 Sep 2017 07:26:51 +0000 (UTC) Received: from wens.csie.org (mirror2.csie.ntu.edu.tw [140.112.30.76]) by lists.denx.de (Postfix) with ESMTPS id E227FC21E3C for ; Fri, 22 Sep 2017 07:26:46 +0000 (UTC) Received: by wens.csie.org (Postfix, from userid 1000) id CBFDA600A3; Fri, 22 Sep 2017 15:26:36 +0800 (CST) From: Chen-Yu Tsai To: u-boot@lists.denx.de Date: Fri, 22 Sep 2017 15:26:33 +0800 Message-Id: <20170922072635.32105-8-wens@csie.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20170922072635.32105-1-wens@csie.org> References: <20170922072635.32105-1-wens@csie.org> Cc: Joe Hershberger , Jagan Teki , Maxime Ripard Subject: [U-Boot] [PATCH 7/9] net: sun8i_emac: Fix build for non-H3/H5 SoCs X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Only the H3/H5 SoCs have an internal PHY and its related clock and reset controls. Use an #ifdef to guard the internal PHY control code block so it can be built for other SoCs, such as the A83T or A64. Signed-off-by: Chen-Yu Tsai Acked-by: Maxime Ripard Reviewed-by: Joe Hershberger --- drivers/net/sun8i_emac.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c index 5fa1b4c170d7..0a98a04967da 100644 --- a/drivers/net/sun8i_emac.c +++ b/drivers/net/sun8i_emac.c @@ -616,6 +616,8 @@ static void sun8i_emac_board_setup(struct emac_eth_dev *priv) { struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; +#ifdef CONFIG_MACH_SUNXI_H3_H5 + /* Only H3/H5 have clock controls for internal EPHY */ if (priv->use_internal_phy) { /* Set clock gating for ephy */ setbits_le32(&ccm->bus_gate4, BIT(AHB_GATE_OFFSET_EPHY)); @@ -623,6 +625,7 @@ static void sun8i_emac_board_setup(struct emac_eth_dev *priv) /* Deassert EPHY */ setbits_le32(&ccm->ahb_reset2_cfg, BIT(AHB_RESET_OFFSET_EPHY)); } +#endif /* Set clock gating for emac */ setbits_le32(&ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_GMAC));