From patchwork Fri Jul 28 17:02:15 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 794986 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3xJwBw2wykz9s0Z for ; Sat, 29 Jul 2017 03:02:47 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id D23E0C21DED; Fri, 28 Jul 2017 17:02:42 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-5.0 required=5.0 tests=RCVD_IN_DNSWL_HI autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id BE8D7C21C3F; Fri, 28 Jul 2017 17:02:39 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id EFB4DC21C3F; Fri, 28 Jul 2017 17:02:37 +0000 (UTC) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by lists.denx.de (Postfix) with ESMTPS id 0E2B2C21C39 for ; Fri, 28 Jul 2017 17:02:35 +0000 (UTC) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 28 Jul 2017 10:02:18 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.40,425,1496127600"; d="scan'208";a="998318759" Received: from black.fi.intel.com ([10.237.72.28]) by orsmga003.jf.intel.com with ESMTP; 28 Jul 2017 10:02:16 -0700 Received: by black.fi.intel.com (Postfix, from userid 1003) id CC955D8; Fri, 28 Jul 2017 20:02:15 +0300 (EEST) From: Andy Shevchenko To: Bin Meng , u-boot@lists.denx.de, Simon Glass , Alexander Graf Date: Fri, 28 Jul 2017 20:02:15 +0300 Message-Id: <20170728170215.53700-1-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.13.2 Cc: Andy Shevchenko Subject: [U-Boot] [PATCH v1] x86: Make table address selectable X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Some firmwares might have another window for generated tables. So, introduce two configuration options to select start address and maximum length for the generated tables. Signed-off-by: Andy Shevchenko Reviewed-by: Bin Meng --- arch/x86/Kconfig | 13 +++++++++++++ arch/x86/include/asm/tables.h | 9 ++------- 2 files changed, 15 insertions(+), 7 deletions(-) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 5c8dc822ef..c26710b484 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -542,6 +542,19 @@ config VGA_BIOS_ADDR address of 0xfff90000 indicates that the image will be put at offset 0x90000 from the beginning of a 1MB flash device. +config ROM_TABLE_ADDR + hex + default 0xf0000 + help + All x86 tables happen to like the address range from 0x0f0000 + to 0x100000. We use 0xf0000 as the starting address to store + those tables, including PIRQ routing table, Multi-Processor + table and ACPI table. + +config ROM_TABLE_SIZE + hex + default 0x10000 + menu "System tables" depends on !EFI && !SYS_COREBOOT diff --git a/arch/x86/include/asm/tables.h b/arch/x86/include/asm/tables.h index 9e8208ba2b..c784a2aeec 100644 --- a/arch/x86/include/asm/tables.h +++ b/arch/x86/include/asm/tables.h @@ -9,13 +9,8 @@ #include -/* - * All x86 tables happen to like the address range from 0xf0000 to 0x100000. - * We use 0xf0000 as the starting address to store those tables, including - * PIRQ routing table, Multi-Processor table and ACPI table. - */ -#define ROM_TABLE_ADDR 0xf0000 -#define ROM_TABLE_END 0xfffff +#define ROM_TABLE_ADDR CONFIG_ROM_TABLE_ADDR +#define ROM_TABLE_END (CONFIG_ROM_TABLE_ADDR + CONFIG_ROM_TABLE_SIZE - 1) #define ROM_TABLE_ALIGN 1024