From patchwork Thu Jul 20 08:12:59 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenyou Yang X-Patchwork-Id: 791501 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3xCnlf675Bz9sNV for ; Thu, 20 Jul 2017 18:54:52 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 1775EC21C97; Thu, 20 Jul 2017 08:54:50 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.3 required=5.0 tests=RCVD_IN_DNSWL_MED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 370BAC21C8B; Thu, 20 Jul 2017 08:19:06 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 870DAC21C40; Thu, 20 Jul 2017 08:19:04 +0000 (UTC) Received: from eusmtp01.atmel.com (eusmtp01.atmel.com [212.144.249.242]) by lists.denx.de (Postfix) with ESMTPS id 51DAFC21C6D for ; Thu, 20 Jul 2017 08:18:00 +0000 (UTC) Received: from apsmtp01.atmel.com (10.168.254.31) by eusmtp01.atmel.com (10.145.145.30) with Microsoft SMTP Server id 14.3.235.1; Thu, 20 Jul 2017 10:17:55 +0200 Received: from shaarm01.corp.atmel.com (10.168.254.13) by apsmtp01.atmel.com (10.168.254.31) with Microsoft SMTP Server id 14.3.235.1; Thu, 20 Jul 2017 16:19:51 +0800 From: Wenyou Yang To: U-Boot Mailing List Date: Thu, 20 Jul 2017 16:12:59 +0800 Message-ID: <20170720081303.9002-3-wenyou.yang@microchip.com> X-Mailer: git-send-email 2.13.0 In-Reply-To: <20170720081303.9002-1-wenyou.yang@microchip.com> References: <20170720081303.9002-1-wenyou.yang@microchip.com> MIME-Version: 1.0 Cc: Marek Vasut Subject: [U-Boot] [PATCH 2/6] ARM: at91: spl: Add mck function to lower rate while switching X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Refer to the commit 70f8c8316ad(PMC: add new mck function to lower rate while switching) from AT91Bootstrap. While switching to a lower clock source, we must switch the clock source first instead of last. Otherwise, we could end up with too high frequency on internal bus and peripherals. This happen on SAMA5D2 as we exit from ROM code @396MHz. Add a function pmc_mck_init_down() to allow this sequence. Signed-off-by: Wenyou Yang --- arch/arm/mach-at91/armv7/clock.c | 36 +++++++++++++++++++++++++++ arch/arm/mach-at91/include/mach/at91_common.h | 1 + 2 files changed, 37 insertions(+) diff --git a/arch/arm/mach-at91/armv7/clock.c b/arch/arm/mach-at91/armv7/clock.c index 2e55953799..8ae01f4020 100644 --- a/arch/arm/mach-at91/armv7/clock.c +++ b/arch/arm/mach-at91/armv7/clock.c @@ -150,6 +150,42 @@ void at91_mck_init(u32 mckr) ; } +void at91_mck_init_down(u32 mckr) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + u32 tmp; + + tmp = readl(&pmc->mckr); + tmp &= (~AT91_PMC_MCKR_CSS_MASK); + tmp |= (mckr & AT91_PMC_MCKR_CSS_MASK); + writel(tmp, &pmc->mckr); + + while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) + ; + +#ifdef CPU_HAS_H32MXDIV + tmp = readl(&pmc->mckr); + tmp &= (~AT91_PMC_MCKR_H32MXDIV); + tmp |= (mckr & AT91_PMC_MCKR_H32MXDIV); + writel(tmp, &pmc->mckr); +#endif + + tmp = readl(&pmc->mckr); + tmp &= (~AT91_PMC_MCKR_PLLADIV_MASK); + tmp |= (mckr & AT91_PMC_MCKR_PLLADIV_MASK); + writel(tmp, &pmc->mckr); + + tmp = readl(&pmc->mckr); + tmp &= (~AT91_PMC_MCKR_MDIV_MASK); + tmp |= (mckr & AT91_PMC_MCKR_MDIV_MASK); + writel(tmp, &pmc->mckr); + + tmp = readl(&pmc->mckr); + tmp &= (~AT91_PMC_MCKR_PRES_MASK); + tmp |= (mckr & AT91_PMC_MCKR_PRES_MASK); + writel(tmp, &pmc->mckr); +} + int at91_enable_periph_generated_clk(u32 id, u32 clk_source, u32 div) { struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; diff --git a/arch/arm/mach-at91/include/mach/at91_common.h b/arch/arm/mach-at91/include/mach/at91_common.h index 0742ffc56f..381312709f 100644 --- a/arch/arm/mach-at91/include/mach/at91_common.h +++ b/arch/arm/mach-at91/include/mach/at91_common.h @@ -25,6 +25,7 @@ void at91_lcd_hw_init(void); void at91_plla_init(u32 pllar); void at91_pllb_init(u32 pllar); void at91_mck_init(u32 mckr); +void at91_mck_init_down(u32 mckr); void at91_pmc_init(void); void mem_init(void); void at91_phy_reset(void);