From patchwork Wed Jul 5 17:33:20 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 784788 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3x2nz552Rkz9s4s for ; Thu, 6 Jul 2017 03:33:36 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 0BE70C21EB9; Wed, 5 Jul 2017 17:33:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-5.0 required=5.0 tests=RCVD_IN_DNSWL_HI, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 310F6C21C41; Wed, 5 Jul 2017 17:33:29 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id A005FC21C41; Wed, 5 Jul 2017 17:33:27 +0000 (UTC) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by lists.denx.de (Postfix) with ESMTPS id D79D0C21C2F for ; Wed, 5 Jul 2017 17:33:26 +0000 (UTC) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 05 Jul 2017 10:33:24 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="5.40,312,1496127600"; d="scan'208"; a="1168410953" Received: from black.fi.intel.com ([10.237.72.28]) by fmsmga001.fm.intel.com with ESMTP; 05 Jul 2017 10:33:21 -0700 Received: by black.fi.intel.com (Postfix, from userid 1003) id F260FD7; Wed, 5 Jul 2017 20:33:20 +0300 (EEST) From: Andy Shevchenko To: Stefan Roese , Simon Glass , Bin Meng , u-boot@lists.denx.de, Lukasz Majewski , Tom Rini Date: Wed, 5 Jul 2017 20:33:20 +0300 Message-Id: <20170705173320.72773-1-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.11.0 Cc: Andy Shevchenko Subject: [U-Boot] [PATCH v3] watchdog: Introduce watchdog driver for Intel Tangier X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Felipe Balbi Add watchdog driver for Intel Tangier based platforms. Signed-off-by: Vincent Tinelli Signed-off-by: Felipe Balbi Signed-off-by: Andy Shevchenko Reviewed-by: Bin Meng --- In v3: - protect against overflow in hw_watchdog_reset() drivers/watchdog/Kconfig | 11 ++++++- drivers/watchdog/Makefile | 1 + drivers/watchdog/tangier_wdt.c | 71 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 82 insertions(+), 1 deletion(-) create mode 100644 drivers/watchdog/tangier_wdt.c diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index b911233db3..6cbc450b3c 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -19,7 +19,16 @@ config OMAP_WATCHDOG default y if AM33XX help Say Y here to enable the OMAP3+ watchdog driver. - + +config TANGIER_WATCHDOG + bool "Intel Tangier watchdog" + depends on INTEL_MID + select HW_WATCHDOG + help + This enables support for watchdog controller available on + Intel Tangier SoC. If you're using a board with Intel Tangier + SoC, say Y here. + config ULP_WATCHDOG bool "i.MX7ULP watchdog" help diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index 4b19e4ccf6..8a3fa1da67 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_S5P) += s5p_wdt.o obj-$(CONFIG_XILINX_TB_WATCHDOG) += xilinx_tb_wdt.o obj-$(CONFIG_OMAP_WATCHDOG) += omap_wdt.o obj-$(CONFIG_DESIGNWARE_WATCHDOG) += designware_wdt.o +obj-$(CONFIG_TANGIER_WATCHDOG) += tangier_wdt.o obj-$(CONFIG_ULP_WATCHDOG) += ulp_wdog.o obj-$(CONFIG_WDT) += wdt-uclass.o obj-$(CONFIG_WDT_SANDBOX) += sandbox_wdt.o diff --git a/drivers/watchdog/tangier_wdt.c b/drivers/watchdog/tangier_wdt.c new file mode 100644 index 0000000000..9cf4bafa92 --- /dev/null +++ b/drivers/watchdog/tangier_wdt.c @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2017 Intel Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include + +/* Hardware timeout in seconds */ +#define WDT_PRETIMEOUT 15 +#define WDT_TIMEOUT_MIN (1 + WDT_PRETIMEOUT) +#define WDT_TIMEOUT_MAX 170 +#define WDT_DEFAULT_TIMEOUT 90 + +#ifndef CONFIG_WATCHDOG_TIMEOUT_MSECS +#define WATCHDOG_HEARTBEAT 60000 +#else +#define WATCHDOG_HEARTBEAT CONFIG_WATCHDOG_TIMEOUT_MSECS +#endif + +enum { + SCU_WATCHDOG_START = 0, + SCU_WATCHDOG_STOP = 1, + SCU_WATCHDOG_KEEPALIVE = 2, + SCU_WATCHDOG_SET_ACTION_ON_TIMEOUT = 3, +}; + +void hw_watchdog_reset(void) +{ + static unsigned long last; + unsigned long now; + + if (gd->timer) + now = timer_get_us(); + else + now = rdtsc() / 1000; + + /* Do not flood SCU */ + if (last > now) + last = 0; + + if (unlikely((now - last) > (WDT_PRETIMEOUT / 2) * 1000000)) { + last = now; + scu_ipc_simple_command(IPCMSG_WATCHDOG_TIMER, SCU_WATCHDOG_KEEPALIVE); + } +} + +int hw_watchdog_disable(void) +{ + return scu_ipc_simple_command(IPCMSG_WATCHDOG_TIMER, SCU_WATCHDOG_STOP); +} + +void hw_watchdog_init(void) +{ + u32 timeout = WATCHDOG_HEARTBEAT / 1000; + int in_size; + struct ipc_wd_start { + u32 pretimeout; + u32 timeout; + } ipc_wd_start = { timeout - WDT_PRETIMEOUT, timeout }; + + /* + * SCU expects the input size for watchdog IPC + * to be based on 4 bytes + */ + in_size = DIV_ROUND_UP(sizeof(ipc_wd_start), 4); + + scu_ipc_command(IPCMSG_WATCHDOG_TIMER, SCU_WATCHDOG_START, + (u32 *)&ipc_wd_start, in_size, NULL, 0); +}