From patchwork Wed Jun 7 00:47:16 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Icenowy Zheng X-Patchwork-Id: 772120 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3wj93p0GNBz9s82 for ; Wed, 7 Jun 2017 10:51:33 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id BC9FBC21CE7; Wed, 7 Jun 2017 00:48:46 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 8EE35C21C5E; Wed, 7 Jun 2017 00:48:28 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 36F13C21C85; Wed, 7 Jun 2017 00:48:13 +0000 (UTC) Received: from catfish.ash.relay.mailchannels.net (catfish.ash.relay.mailchannels.net [23.83.222.32]) by lists.denx.de (Postfix) with ESMTPS id F3F51C21CA9 for ; Wed, 7 Jun 2017 00:48:08 +0000 (UTC) X-Sender-Id: lmn-tzduiowcrqmw|x-authsender|icenowy@aosc.io Received: from relay.mailchannels.net (localhost [127.0.0.1]) by relay.mailchannels.net (Postfix) with ESMTP id 20E5C125577; Wed, 7 Jun 2017 00:48:05 +0000 (UTC) Received: from hermes.aosc.io (unknown [100.96.136.220]) (Authenticated sender: lmn-TZDUIOWCRQMW) by relay.mailchannels.net (Postfix) with ESMTPA id 2DB31125530; Wed, 7 Jun 2017 00:48:04 +0000 (UTC) X-Sender-Id: lmn-tzduiowcrqmw|x-authsender|icenowy@aosc.io Received: from hermes.aosc.io (hermes.aosc.io [172.20.88.133]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384) by 0.0.0.0:2500 (trex/5.9.4); Wed, 07 Jun 2017 00:48:05 +0000 X-MC-Relay: Neutral X-MailChannels-SenderId: lmn-tzduiowcrqmw|x-authsender|icenowy@aosc.io X-MailChannels-Auth-Id: lmn-TZDUIOWCRQMW X-Daffy-Befitting: 22b8b14963aed154_1496796484797_2465446823 X-MC-Loop-Signature: 1496796484797:2650695277 X-MC-Ingress-Time: 1496796484796 Received: from localhost (localhost [127.0.0.1]) (Authenticated sender: icenowy@aosc.io) by hermes.aosc.io (Postfix) with ESMTPSA id 1DC4750E9E; Wed, 7 Jun 2017 00:47:59 +0000 (UTC) From: Icenowy Zheng To: Jagan Teki , Maxime Ripard , Chen-Yu Tsai Date: Wed, 7 Jun 2017 08:47:16 +0800 Message-Id: <20170607004721.24194-4-icenowy@aosc.io> In-Reply-To: <20170607004721.24194-1-icenowy@aosc.io> References: <20170607004721.24194-1-icenowy@aosc.io> Cc: u-boot@lists.denx.de, linux-sunxi@googlegroups.com, Icenowy Zheng Subject: [U-Boot] [RFC PATCH 3/8] sun8i: Add a macro to read the silicon revision X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: "tpearson@raptorengineering.com" According to the user manuals released by Allwinner, the low 8-bit of the 0x24 register in "System Control" (marked SRAMC in U-Boot source as it controls some SRAMs' functionality since A10) is the silicon revision of the chip. This data is now important for A83T: according to the BSP source A83T have two revisions: Revision A (with revision ID 0) and Revision B (with revision ID 1); and revision B requires a SMP bringup workaround. Print the revision number when the SoC is A83T, as it does matter there. Signed-off-by: Timothy Pearson [Icenowy: convert to macro so that it can be reused in PSCI code] Signed-off-by: Icenowy Zheng Reviewed-by: Chen-Yu Tsai --- arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 7 +++++++ arch/arm/mach-sunxi/cpu_info.c | 2 +- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h index 6aa5e91ada..a96680d8e8 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h @@ -205,6 +205,13 @@ void sunxi_board_init(void); void sunxi_reset(void); int sunxi_get_ss_bonding_id(void); int sunxi_get_sid(unsigned int *sid); + +/* + * Implement it as a macro, because it's used both in PSCI source code + * and normal U-Boot source code. + */ +#define sunxi_get_revision() (readl(SUNXI_SRAMC_BASE + 0x24) & 0xff) + #endif /* __ASSEMBLY__ */ #endif /* _SUNXI_CPU_SUN4I_H */ diff --git a/arch/arm/mach-sunxi/cpu_info.c b/arch/arm/mach-sunxi/cpu_info.c index 25a5ec26a0..4236ab8f11 100644 --- a/arch/arm/mach-sunxi/cpu_info.c +++ b/arch/arm/mach-sunxi/cpu_info.c @@ -84,7 +84,7 @@ int print_cpuinfo(void) #elif defined CONFIG_MACH_SUN8I_A33 printf("CPU: Allwinner A33 (SUN8I %04x)\n", sunxi_get_sram_id()); #elif defined CONFIG_MACH_SUN8I_A83T - printf("CPU: Allwinner A83T (SUN8I %04x)\n", sunxi_get_sram_id()); + printf("CPU: Allwinner A83T (SUN8I %04x rev. %x)\n", sunxi_get_sram_id(), sunxi_get_revision()); #elif defined CONFIG_MACH_SUN8I_H3 printf("CPU: Allwinner H3 (SUN8I %04x)\n", sunxi_get_sram_id()); #elif defined CONFIG_MACH_SUN8I_R40