From patchwork Fri May 19 14:31:02 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 764715 X-Patchwork-Delegate: twarren@nvidia.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3wTrTk3jb9z9s5j for ; Sat, 20 May 2017 00:46:18 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=google.com header.i=@google.com header.b="i/oOw0F5"; dkim-atps=neutral Received: by lists.denx.de (Postfix, from userid 105) id 427B1C2254F; Fri, 19 May 2017 14:36:28 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 1FB82C223E8; Fri, 19 May 2017 14:32:43 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id A8B7BC2222E; Fri, 19 May 2017 14:31:38 +0000 (UTC) Received: from mail-oi0-f43.google.com (mail-oi0-f43.google.com [209.85.218.43]) by lists.denx.de (Postfix) with ESMTPS id CE553C222A4 for ; Fri, 19 May 2017 14:31:34 +0000 (UTC) Received: by mail-oi0-f43.google.com with SMTP id b204so94147362oii.1 for ; Fri, 19 May 2017 07:31:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=9q1amOpUG4fIKpQcvQjogUFlGKXst4nVs3XFzEDnDO4=; b=i/oOw0F5kjW3Dle4EVABrQH/ymiRyXanXMfx1lTFPNJEL+7Pzucnr+ghoOjuBDpPqx cuMyURoImOATEmmcT1F6XBInPRBN7qqVlzMxFscpDVgoLbawgQ86VRGrjRLsca3jRx15 g1hgbFZ/eqqztXk1m6BHaZsWA8SW1cVm12SbBWXOXquUxCoA0EAivLrhRAtzHLuxC1RR RNdSj+Ss8hfuM6v2g82wYa0Z6DETK2+KBcKwhdF6NNxFJCNt21RfJrLQuZfWP/9koo/A joS7tMyXp0/4TS7wmVbdY3wMY+9mxv+zRjzeasLD9Fmd3K4KYDC0QXuG9hlb7wVMYHOy F/6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=9q1amOpUG4fIKpQcvQjogUFlGKXst4nVs3XFzEDnDO4=; b=WF+xaU6nCD7WpZB2hwXTePA80/BhdQ0SXPArlWtIqmny0mwPjFPahDPGLm+x+5L2Wn Fbcwp5XL08+GSR28ZOj+us9Ld1OoVxya/+By0lNNH/DynhJJRqpAeCnBeJ5ktEQzThFB +85Cg3GUS2GaMJwLziMJgsXfUci+FkA5CpDAk9Knzwlle+b187+2A4PaVvMtMf2dxcds nWo9hjwOTy9DXHKVzn58BlmH2lRC3GYYd5fUC4Cv3Gsobid8Bo3tcaFsySQyTTq543la pYHKhp+XB12gZMAFQFEll4t3V0HHMBIWtmkzNpQ0aDFilcHvJyt2fakSWXTQ8xhh9nK+ RoGw== X-Gm-Message-State: AODbwcD/ABYaKBxx7XCvHxRSuaefIxGame3860LUAWjMCT11sVj5qQ3I BwSlN5ddZWTgnWDE X-Received: by 10.202.81.12 with SMTP id f12mr5573317oib.66.1495204293420; Fri, 19 May 2017 07:31:33 -0700 (PDT) Received: from kaki.bld.corp.google.com ([100.100.184.96]) by smtp.gmail.com with ESMTPSA id k54sm4245393otd.25.2017.05.19.07.31.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 19 May 2017 07:31:32 -0700 (PDT) Received: by kaki.bld.corp.google.com (Postfix, from userid 121222) id 4DFF440563; Fri, 19 May 2017 08:31:32 -0600 (MDT) From: Simon Glass To: U-Boot Mailing List Date: Fri, 19 May 2017 08:31:02 -0600 Message-Id: <20170519143109.21683-20-sjg@chromium.org> X-Mailer: git-send-email 2.13.0.303.g4ebf302169-goog In-Reply-To: <20170519143109.21683-1-sjg@chromium.org> References: <20170519143109.21683-1-sjg@chromium.org> Cc: Tom Rini , Lukasz Majewski Subject: [U-Boot] [PATCH 19/26] power: Add a GPIO driver for the as3722 PMIC X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This pmic includes GPIOs which should have their own driver. Add a driver to support these. Signed-off-by: Simon Glass Reviewed-by: Lukasz Majewski --- drivers/power/pmic/as3722_gpio.c | 120 +++++++++++++++++++++++++++++++++++++++ include/power/as3722.h | 5 ++ 2 files changed, 125 insertions(+) create mode 100644 drivers/power/pmic/as3722_gpio.c diff --git a/drivers/power/pmic/as3722_gpio.c b/drivers/power/pmic/as3722_gpio.c new file mode 100644 index 0000000000..d0b681ca4a --- /dev/null +++ b/drivers/power/pmic/as3722_gpio.c @@ -0,0 +1,120 @@ +/* + * Copyright (C) 2014 NVIDIA Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +#define NUM_GPIOS 8 + +int as3722_gpio_configure(struct udevice *pmic, unsigned int gpio, + unsigned long flags) +{ + u8 value = 0; + int err; + + if (flags & AS3722_GPIO_OUTPUT_VDDH) + value |= AS3722_GPIO_CONTROL_MODE_OUTPUT_VDDH; + + if (flags & AS3722_GPIO_INVERT) + value |= AS3722_GPIO_CONTROL_INVERT; + + err = pmic_reg_write(pmic, AS3722_GPIO_CONTROL(gpio), value); + if (err) { + error("failed to configure GPIO#%u: %d", gpio, err); + return err; + } + + return 0; +} + +static int as3722_gpio_set_value(struct udevice *dev, unsigned int gpio, + int level) +{ + struct udevice *pmic = dev_get_parent(dev); + const char *l; + u8 value; + int err; + + if (gpio >= NUM_GPIOS) + return -EINVAL; + + err = pmic_reg_read(pmic, AS3722_GPIO_SIGNAL_OUT); + if (err < 0) { + error("failed to read GPIO signal out register: %d", err); + return err; + } + value = err; + + if (level == 0) { + value &= ~(1 << gpio); + l = "low"; + } else { + value |= 1 << gpio; + l = "high"; + } + + err = pmic_reg_write(pmic, AS3722_GPIO_SIGNAL_OUT, value); + if (err) { + error("failed to set GPIO#%u %s: %d", gpio, l, err); + return err; + } + + return 0; +} + +int as3722_gpio_direction_output(struct udevice *dev, unsigned int gpio, + int value) +{ + struct udevice *pmic = dev_get_parent(dev); + int err; + + if (gpio > 7) + return -EINVAL; + + if (value == 0) + value = AS3722_GPIO_CONTROL_MODE_OUTPUT_VDDL; + else + value = AS3722_GPIO_CONTROL_MODE_OUTPUT_VDDH; + + err = pmic_reg_write(pmic, AS3722_GPIO_CONTROL(gpio), value); + if (err) { + error("failed to configure GPIO#%u as output: %d", gpio, err); + return err; + } + + err = as3722_gpio_set_value(pmic, gpio, value); + if (err < 0) { + error("failed to set GPIO#%u high: %d", gpio, err); + return err; + } + + return 0; +} + +static int as3722_gpio_probe(struct udevice *dev) +{ + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + + uc_priv->gpio_count = NUM_GPIOS; + uc_priv->bank_name = "as3722_"; + + return 0; +} + +static const struct dm_gpio_ops gpio_as3722_ops = { + .direction_output = as3722_gpio_direction_output, + .set_value = as3722_gpio_set_value, +}; + +U_BOOT_DRIVER(gpio_as3722) = { + .name = "gpio_as3722", + .id = UCLASS_GPIO, + .ops = &gpio_as3722_ops, + .probe = as3722_gpio_probe, +}; diff --git a/include/power/as3722.h b/include/power/as3722.h index 14afa0c81a..713e79840f 100644 --- a/include/power/as3722.h +++ b/include/power/as3722.h @@ -20,6 +20,11 @@ #define AS3722_ASIC_ID1 0x90 #define AS3722_ASIC_ID2 0x91 +#define AS3722_GPIO_CONTROL(n) (0x08 + (n)) +#define AS3722_GPIO_CONTROL_MODE_OUTPUT_VDDH (1 << 0) +#define AS3722_GPIO_CONTROL_MODE_OUTPUT_VDDL (7 << 0) +#define AS3722_GPIO_CONTROL_INVERT (1 << 7) + struct udevice; int as3722_init(struct udevice **devp);