From patchwork Wed Apr 26 14:49:56 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Icenowy Zheng X-Patchwork-Id: 755510 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3wCjhR0tjbz9s82 for ; Thu, 27 Apr 2017 00:51:35 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id CC95AC21C53; Wed, 26 Apr 2017 14:50:55 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id EF45BC21CAB; Wed, 26 Apr 2017 14:50:46 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id DE429C21C40; Wed, 26 Apr 2017 14:50:40 +0000 (UTC) Received: from eastern.birch.relay.mailchannels.net (eastern.birch.relay.mailchannels.net [23.83.209.55]) by lists.denx.de (Postfix) with ESMTPS id 3DBA0C21C82 for ; Wed, 26 Apr 2017 14:50:35 +0000 (UTC) X-Sender-Id: lmn-tzduiowcrqmw|x-authsender|icenowy@aosc.io Received: from relay.mailchannels.net (localhost [127.0.0.1]) by relay.mailchannels.net (Postfix) with ESMTP id 8CF828A45D7; Wed, 26 Apr 2017 14:50:32 +0000 (UTC) Received: from hermes.aosc.io (unknown [100.96.135.123]) by relay.mailchannels.net (Postfix) with ESMTPA id A865A8A5F9E; Wed, 26 Apr 2017 14:50:31 +0000 (UTC) X-Sender-Id: lmn-tzduiowcrqmw|x-authsender|icenowy@aosc.io Received: from hermes.aosc.io (hermes.aosc.io [172.20.82.168]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384) by 0.0.0.0:2500 (trex/5.9.2); Wed, 26 Apr 2017 14:50:32 +0000 X-MC-Relay: Neutral X-MailChannels-SenderId: lmn-tzduiowcrqmw|x-authsender|icenowy@aosc.io X-MailChannels-Auth-Id: lmn-TZDUIOWCRQMW X-Drop-Wide-Eyed: 5687ffdc295d964f_1493218232391_4286334137 X-MC-Loop-Signature: 1493218232391:3562823811 X-MC-Ingress-Time: 1493218232391 Received: from localhost (localhost [127.0.0.1]) (Authenticated sender: icenowy@aosc.io) by hermes.aosc.io (Postfix) with ESMTPSA id 86B0A492EB; Wed, 26 Apr 2017 14:50:27 +0000 (UTC) From: Icenowy Zheng To: Jagan Teki , Maxime Ripard , Andre Przywara , Jens Kuske Date: Wed, 26 Apr 2017 22:49:56 +0800 Message-Id: <20170426145007.39563-2-icenowy@aosc.io> In-Reply-To: <20170426145007.39563-1-icenowy@aosc.io> References: <20170426145007.39563-1-icenowy@aosc.io> Cc: u-boot@lists.denx.de, linux-sunxi@googlegroups.com, Icenowy Zheng Subject: [U-Boot] [PATCH 01/12] sunxi: makes an invisible option for H3-like DRAM controllers X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Icenowy Zheng Allwinner SoCs after H3 (e.g. A64, H5, R40, V3s) uses a H3-like DesignWare DRAM controller, which do not have official free DRAM initialization code, but can use modified dram_sun8i_h3.c. Add a invisible option for easier DRAM initialization code reuse. Signed-off-by: Icenowy Zheng Acked-by: Maxime Ripard --- arch/arm/include/asm/arch-sunxi/dram.h | 6 ++---- .../asm/arch-sunxi/{dram_sun8i_h3.h => dram_sunxi_dw.h} | 0 arch/arm/mach-sunxi/Makefile | 4 +--- arch/arm/mach-sunxi/{dram_sun8i_h3.c => dram_sunxi_dw.c} | 0 board/sunxi/Kconfig | 10 ++++++++++ 5 files changed, 13 insertions(+), 7 deletions(-) rename arch/arm/include/asm/arch-sunxi/{dram_sun8i_h3.h => dram_sunxi_dw.h} (100%) rename arch/arm/mach-sunxi/{dram_sun8i_h3.c => dram_sunxi_dw.c} (100%) diff --git a/arch/arm/include/asm/arch-sunxi/dram.h b/arch/arm/include/asm/arch-sunxi/dram.h index f452f889f9..80abac95b8 100644 --- a/arch/arm/include/asm/arch-sunxi/dram.h +++ b/arch/arm/include/asm/arch-sunxi/dram.h @@ -24,10 +24,8 @@ #include #elif defined(CONFIG_MACH_SUN8I_A83T) #include -#elif defined(CONFIG_MACH_SUNXI_H3_H5) || \ - defined(CONFIG_MACH_SUN8I_R40) || \ - defined(CONFIG_MACH_SUN50I) -#include +#elif defined(CONFIG_SUNXI_DRAM_DW) +#include #elif defined(CONFIG_MACH_SUN9I) #include #else diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun8i_h3.h b/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h similarity index 100% rename from arch/arm/include/asm/arch-sunxi/dram_sun8i_h3.h rename to arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile index 5510aa5435..41cee26765 100644 --- a/arch/arm/mach-sunxi/Makefile +++ b/arch/arm/mach-sunxi/Makefile @@ -48,8 +48,6 @@ obj-$(CONFIG_MACH_SUN7I) += dram_sun4i.o obj-$(CONFIG_MACH_SUN8I_A23) += dram_sun8i_a23.o obj-$(CONFIG_MACH_SUN8I_A33) += dram_sun8i_a33.o obj-$(CONFIG_MACH_SUN8I_A83T) += dram_sun8i_a83t.o -obj-$(CONFIG_MACH_SUNXI_H3_H5) += dram_sun8i_h3.o -obj-$(CONFIG_MACH_SUN8I_R40) += dram_sun8i_h3.o +obj-$(CONFIG_SUNXI_DRAM_DW) += dram_sunxi_dw.o obj-$(CONFIG_MACH_SUN9I) += dram_sun9i.o -obj-$(CONFIG_MACH_SUN50I) += dram_sun8i_h3.o endif diff --git a/arch/arm/mach-sunxi/dram_sun8i_h3.c b/arch/arm/mach-sunxi/dram_sunxi_dw.c similarity index 100% rename from arch/arm/mach-sunxi/dram_sun8i_h3.c rename to arch/arm/mach-sunxi/dram_sunxi_dw.c diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index b47034f417..f1338dd539 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -55,10 +55,18 @@ config SUNXI_GEN_SUN6I separate ahb reset control registers, custom pmic bus, new style watchdog, etc. +config SUNXI_DRAM_DW + bool + ---help--- + Select this for sunxi SoCs which uses a DRAM controller like the + DesignWare controller used in H3, mainly SoCs after H3, which do + not have official open-source DRAM initialization code, but can + use modified H3 DRAM initialization code. config MACH_SUNXI_H3_H5 bool select SUNXI_DE2 + select SUNXI_DRAM_DW select SUNXI_GEN_SUN6I select SUPPORT_SPL @@ -143,6 +151,7 @@ config MACH_SUN8I_R40 select ARCH_SUPPORT_PSCI select SUNXI_GEN_SUN6I select SUPPORT_SPL + select SUNXI_DRAM_DW config MACH_SUN8I_V3S bool "sun8i (Allwinner V3s)" @@ -167,6 +176,7 @@ config MACH_SUN50I select SUNXI_GEN_SUN6I select SUNXI_HIGH_SRAM select SUPPORT_SPL + select SUNXI_DRAM_DW config MACH_SUN50I_H5 bool "sun50i (Allwinner H5)"