From patchwork Tue Mar 21 14:27:45 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Roese X-Patchwork-Id: 741597 X-Patchwork-Delegate: sr@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3vnbGJ2thrz9s7t for ; Wed, 22 Mar 2017 01:45:44 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 1C51CC21D51; Tue, 21 Mar 2017 14:33:32 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id DB083C21D58; Tue, 21 Mar 2017 14:28:40 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 12978C21D68; Tue, 21 Mar 2017 14:28:18 +0000 (UTC) Received: from mx2.mailbox.org (mx2.mailbox.org [80.241.60.215]) by lists.denx.de (Postfix) with ESMTPS id F3111C21D1C for ; Tue, 21 Mar 2017 14:28:13 +0000 (UTC) Received: from smtp1.mailbox.org (smtp1.mailbox.org [80.241.60.240]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx2.mailbox.org (Postfix) with ESMTPS id BFA3445A66; Tue, 21 Mar 2017 15:28:13 +0100 (CET) X-Virus-Scanned: amavisd-new at heinlein-support.de Received: from smtp1.mailbox.org ([80.241.60.240]) by spamfilter03.heinlein-hosting.de (spamfilter03.heinlein-hosting.de [80.241.56.117]) (amavisd-new, port 10030) with ESMTP id KVwSXpcw_i4X; Tue, 21 Mar 2017 15:28:12 +0100 (CET) From: Stefan Roese To: u-boot@lists.denx.de Date: Tue, 21 Mar 2017 15:27:45 +0100 Message-Id: <20170321142802.24276-25-sr@denx.de> In-Reply-To: <20170321142802.24276-1-sr@denx.de> References: <20170321142802.24276-1-sr@denx.de> Cc: Nadav Haklai , Stefan Chulski , Thomas Petazzoni Subject: [U-Boot] [PATCH v1 24/41] net: mvpp2: adapt rxq distribution to PPv2.2 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Thomas Petazzoni In PPv2.1, we have a maximum of 8 RXQs per port, with a default of 4 RXQs per port, and we were assigning RXQs 0->3 to the first port, 4->7 to the second port, 8->11 to the third port, etc. In PPv2.2, we have a maximum of 32 RXQs per port, and we must allocate RXQs from the range of 32 RXQs available for each port. So port 0 must use RXQs in the range 0->31, port 1 in the range 32->63, etc. This commit adapts the mvpp2 to this difference between PPv2.1 and PPv2.2: - The constant definition MVPP2_MAX_RXQ is replaced by a new field 'max_port_rxqs' in 'struct mvpp2', which stores the maximum number of RXQs per port. This field is initialized during ->probe() depending on the IP version. - MVPP2_RXQ_TOTAL_NUM is removed, and instead we calculate the total number of RXQs by multiplying the number of ports by the maximum of RXQs per port. This was anyway used in only one place. - In mvpp2_port_probe(), the calculation of port->first_rxq is adjusted to cope with the different allocation strategy between PPv2.1 and PPv2.2. Due to this change, the 'next_first_rxq' argument of this function is no longer needed and is removed. Signed-off-by: Thomas Petazzoni Signed-off-by: Stefan Roese Acked-by: Joe Hershberger --- drivers/net/mvpp2.c | 33 ++++++++++++++++++--------------- 1 file changed, 18 insertions(+), 15 deletions(-) diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c index 567324bed9..745e46e4b4 100644 --- a/drivers/net/mvpp2.c +++ b/drivers/net/mvpp2.c @@ -454,9 +454,6 @@ do { \ /* Maximum number of TXQs used by single port */ #define MVPP2_MAX_TXQ 8 -/* Maximum number of RXQs used by single port */ -#define MVPP2_MAX_RXQ 8 - /* Default number of TXQs in use */ #define MVPP2_DEFAULT_TXQ 1 @@ -464,9 +461,6 @@ do { \ #define MVPP2_DEFAULT_RXQ 1 #define CONFIG_MV_ETH_RXQ 8 /* increment by 8 */ -/* Total number of RXQs available to all ports */ -#define MVPP2_RXQ_TOTAL_NUM (MVPP2_MAX_PORTS * MVPP2_MAX_RXQ) - /* Max number of Rx descriptors */ #define MVPP2_MAX_RXD 16 @@ -772,6 +766,9 @@ struct mvpp2 { /* HW version */ enum { MVPP21, MVPP22 } hw_version; + /* Maximum number of RXQs per port */ + unsigned int max_port_rxqs; + struct mii_dev *bus; }; @@ -3696,7 +3693,8 @@ static int mvpp2_port_init(struct udevice *dev, struct mvpp2_port *port) struct mvpp2_txq_pcpu *txq_pcpu; int queue, cpu, err; - if (port->first_rxq + rxq_number > MVPP2_RXQ_TOTAL_NUM) + if (port->first_rxq + rxq_number > + MVPP2_MAX_PORTS * priv->max_port_rxqs) return -EINVAL; /* Disable port */ @@ -3804,8 +3802,7 @@ static int mvpp2_port_init(struct udevice *dev, struct mvpp2_port *port) static int mvpp2_port_probe(struct udevice *dev, struct mvpp2_port *port, int port_node, - struct mvpp2 *priv, - int *next_first_rxq) + struct mvpp2 *priv) { int phy_node; u32 id; @@ -3839,7 +3836,10 @@ static int mvpp2_port_probe(struct udevice *dev, port->priv = priv; port->id = id; - port->first_rxq = *next_first_rxq; + if (priv->hw_version == MVPP21) + port->first_rxq = port->id * rxq_number; + else + port->first_rxq = port->id * priv->max_port_rxqs; port->phy_node = phy_node; port->phy_interface = phy_mode; port->phyaddr = phyaddr; @@ -3873,8 +3873,6 @@ static int mvpp2_port_probe(struct udevice *dev, } mvpp2_port_power_up(port); - /* Increment the first Rx queue number to be used by the next port */ - *next_first_rxq += CONFIG_MV_ETH_RXQ; priv->port_list[id] = port; return 0; } @@ -3991,7 +3989,8 @@ static int mvpp2_init(struct udevice *dev, struct mvpp2 *priv) u32 val; /* Checks for hardware constraints (U-Boot uses only one rxq) */ - if ((rxq_number > MVPP2_MAX_RXQ) || (txq_number > MVPP2_MAX_TXQ)) { + if ((rxq_number > priv->max_port_rxqs) || + (txq_number > MVPP2_MAX_TXQ)) { dev_err(&pdev->dev, "invalid queue size parameter\n"); return -EINVAL; } @@ -4385,8 +4384,7 @@ static int mvpp2_probe(struct udevice *dev) return err; } - return mvpp2_port_probe(dev, port, dev_of_offset(dev), priv, - &buffer_loc.first_rxq); + return mvpp2_port_probe(dev, port, dev_of_offset(dev), priv); } static const struct eth_ops mvpp2_ops = { @@ -4474,6 +4472,11 @@ static int mvpp2_base_probe(struct udevice *dev) return PTR_ERR(priv->iface_base); } + if (priv->hw_version == MVPP21) + priv->max_port_rxqs = 8; + else + priv->max_port_rxqs = 32; + /* Finally create and register the MDIO bus driver */ bus = mdio_alloc(); if (!bus) {