From patchwork Sat Mar 11 16:19:32 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Icenowy Zheng X-Patchwork-Id: 737702 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3vgTrk4gr4z9s76 for ; Sun, 12 Mar 2017 03:20:54 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=aosc.xyz header.i=@aosc.xyz header.b="SqtzdQMU"; dkim-atps=neutral Received: by lists.denx.de (Postfix, from userid 105) id 6B0F8C21C6F; Sat, 11 Mar 2017 16:20:39 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 0CD20C21C3D; Sat, 11 Mar 2017 16:20:37 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 34D37C21C76; Sat, 11 Mar 2017 16:20:26 +0000 (UTC) Received: from forward15o.cmail.yandex.net (forward15o.cmail.yandex.net [37.9.109.212]) by lists.denx.de (Postfix) with ESMTPS id 79239C21C44 for ; Sat, 11 Mar 2017 16:20:23 +0000 (UTC) Received: from smtp2j.mail.yandex.net (smtp2j.mail.yandex.net [IPv6:2a02:6b8:0:801::ac]) by forward15o.cmail.yandex.net (Yandex) with ESMTP id 55BE221584; Sat, 11 Mar 2017 19:20:22 +0300 (MSK) Received: from smtp2j.mail.yandex.net (localhost.localdomain [127.0.0.1]) by smtp2j.mail.yandex.net (Yandex) with ESMTP id D58533EC095E; Sat, 11 Mar 2017 19:20:16 +0300 (MSK) Received: by smtp2j.mail.yandex.net (nwsmtp/Yandex) with ESMTPSA id NOvXTVXDuy-KAfa9Etc; Sat, 11 Mar 2017 19:20:14 +0300 (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (Client certificate not present) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=aosc.xyz; s=mail; t=1489249215; bh=3bh493hftHCWcjZv1ZTauwxRaiWgXlwEFdiAB86mrdY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=SqtzdQMU9hGxua96rp/+FJyT5Fs5tHkMrAy+5nXxp55Re4AREA+mEqDVuCa2ZNdkB XYvoC2N+0wqGaOO0HXsenYw4B8ivehu4CeK/F0kr+7iIhotVk+nBbGM7elIJQaxoDn n6lw4ZBkkomZmk7K/fgzn+voavrX6t0qiCRSvejw= Authentication-Results: smtp2j.mail.yandex.net; dkim=pass header.i=@aosc.xyz X-Yandex-ForeignMX: US X-Yandex-Suid-Status: 1 0,1 0,1 0,1 0,1 0,1 0,1 0,1 1130000036118848 From: Icenowy Zheng To: Jagan Teki , Maxime Ripard , Andre Przywara , Jens Kuske , Chen-Yu Tsai Date: Sun, 12 Mar 2017 00:19:32 +0800 Message-Id: <20170311161936.28643-2-icenowy@aosc.xyz> X-Mailer: git-send-email 2.12.0 In-Reply-To: <20170311161936.28643-1-icenowy@aosc.xyz> References: <20170311161936.28643-1-icenowy@aosc.xyz> Cc: u-boot@lists.denx.de, linux-sunxi@googlegroups.com, Icenowy Zheng Subject: [U-Boot] [PATCH 4/8] sunxi: add bank detection code to H3 DRAM initialization code X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Some DDR2 DRAM have only four banks, not eight. Add code to detect this situation. Signed-off-by: Icenowy Zheng Reviewed-by: Andre Przywara --- arch/arm/mach-sunxi/dram_sunxi_dw.c | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-sunxi/dram_sunxi_dw.c b/arch/arm/mach-sunxi/dram_sunxi_dw.c index b08998c0d1..bb4457d2b8 100644 --- a/arch/arm/mach-sunxi/dram_sunxi_dw.c +++ b/arch/arm/mach-sunxi/dram_sunxi_dw.c @@ -31,6 +31,7 @@ struct dram_para { u8 bus_full_width; u8 dual_rank; u8 row_bits; + u8 bank_bits; const u8 dx_read_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE]; const u8 dx_write_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE]; const u8 ac_delays[31]; @@ -367,7 +368,7 @@ static void mctl_set_cr(struct dram_para *para) (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; writel(MCTL_CR_BL8 | MCTL_CR_2T | MCTL_CR_DDR3 | MCTL_CR_INTERLEAVED | - MCTL_CR_EIGHT_BANKS | + (para->bank_bits == 3 ? MCTL_CR_EIGHT_BANKS : MCTL_CR_FOUR_BANKS) | MCTL_CR_BUS_FULL_WIDTH(para->bus_full_width) | (para->dual_rank ? MCTL_CR_DUAL_RANK : MCTL_CR_SINGLE_RANK) | MCTL_CR_PAGE_SIZE(para->page_size) | @@ -575,10 +576,19 @@ static void mctl_auto_detect_dram_size(struct dram_para *para) /* detect row address bits */ para->page_size = 512; para->row_bits = 16; + para->bank_bits = 2; mctl_set_cr(para); for (para->row_bits = 11; para->row_bits < 16; para->row_bits++) - if (mctl_mem_matches((1 << (para->row_bits + 3)) * para->page_size)) + if (mctl_mem_matches((1 << (para->row_bits + para->bank_bits)) * para->page_size)) + break; + + /* detect bank address bits */ + para->bank_bits = 3; + mctl_set_cr(para); + + for (para->bank_bits = 2; para->bank_bits < 3; para->bank_bits++) + if (mctl_mem_matches((1 << para->bank_bits) * para->page_size)) break; /* detect page size */ @@ -640,6 +650,7 @@ unsigned long sunxi_dram_init(void) .dual_rank = 0, .bus_full_width = 1, .row_bits = 15, + .bank_bits = 3, .page_size = 4096, #if defined(CONFIG_MACH_SUN8I_H3) @@ -689,6 +700,6 @@ unsigned long sunxi_dram_init(void) mctl_auto_detect_dram_size(¶); mctl_set_cr(¶); - return (1UL << (para.row_bits + 3)) * para.page_size * - (para.dual_rank ? 2 : 1); + return (1UL << (para.row_bits + para.bank_bits)) * para.page_size * + (para.dual_rank ? 2 : 1); }