From patchwork Sat Feb 18 18:46:22 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Heiko Stuebner X-Patchwork-Id: 729741 X-Patchwork-Delegate: sjg@chromium.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3vRc9N3k0Wz9s8D for ; Mon, 20 Feb 2017 19:24:08 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 4640BB39EF; Mon, 20 Feb 2017 09:21:12 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id dUkWGDhp5CDh; Mon, 20 Feb 2017 09:21:12 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 2D61CB39F3; Mon, 20 Feb 2017 09:17:54 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 400D14A068 for ; Sat, 18 Feb 2017 19:47:43 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id soWCm1eENLun for ; Sat, 18 Feb 2017 19:47:43 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from gloria.sntech.de (gloria.sntech.de [95.129.55.99]) by theia.denx.de (Postfix) with ESMTPS id 15D2B4A026 for ; Sat, 18 Feb 2017 19:47:43 +0100 (CET) Received: from [88.128.80.43] (helo=phil.lufthansa-flynet.com) by gloria.sntech.de with esmtpsa (TLS1.1:DHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.80) (envelope-from ) id 1cfA2l-0004qF-Jr; Sat, 18 Feb 2017 19:47:41 +0100 From: Heiko Stuebner To: sjg@chromium.org Date: Sat, 18 Feb 2017 19:46:22 +0100 Message-Id: <20170218184640.30635-3-heiko@sntech.de> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170218184640.30635-1-heiko@sntech.de> References: <20170218184640.30635-1-heiko@sntech.de> Cc: romain.perier@collabora.com, u-boot@lists.denx.de Subject: [U-Boot] [PATCH v4 02/20] clk: rk3288: limit gpll and cpll init to SPL build X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The gpll and cpll init values are only used in rk_clk_init in the SPL and therefore produce compile time warnings in regular uboot builds. Fix that with an #ifdef. Signed-off-by: Heiko Stuebner Acked-by: Simon Glass --- drivers/clk/rockchip/clk_rk3288.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c index d15504c3aa..78356766a7 100644 --- a/drivers/clk/rockchip/clk_rk3288.c +++ b/drivers/clk/rockchip/clk_rk3288.c @@ -131,8 +131,10 @@ enum { /* Keep divisors as low as possible to reduce jitter and power usage */ static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1); +#ifdef CONFIG_SPL_BUILD static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2); static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2); +#endif static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id, const struct pll_div *div)