From patchwork Fri Feb 17 13:49:00 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 729182 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3vPvX54PmPz9s7x for ; Sat, 18 Feb 2017 00:49:25 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 184D24B01B; Fri, 17 Feb 2017 14:49:21 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id cTE2bDu6uhml; Fri, 17 Feb 2017 14:49:20 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A1BB34AF41; Fri, 17 Feb 2017 14:49:20 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 2949E4A026 for ; Fri, 17 Feb 2017 14:49:10 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 2OAy0Omx0I24 for ; Fri, 17 Feb 2017 14:49:10 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by theia.denx.de (Postfix) with ESMTPS id 6F20F4A99B for ; Fri, 17 Feb 2017 14:49:05 +0100 (CET) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 17 Feb 2017 05:49:03 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.35,171,1484035200"; d="scan'208";a="935082349" Received: from black.fi.intel.com ([10.237.72.28]) by orsmga003.jf.intel.com with ESMTP; 17 Feb 2017 05:49:02 -0800 Received: by black.fi.intel.com (Postfix, from userid 1003) id 5616160E; Fri, 17 Feb 2017 15:49:01 +0200 (EET) From: Andy Shevchenko To: Bin Meng , Simon Glass , u-boot@lists.denx.de, Vincent Tinelli Date: Fri, 17 Feb 2017 16:49:00 +0300 Message-Id: <20170217134900.125003-3-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170217134900.125003-1-andriy.shevchenko@linux.intel.com> References: <20170217134900.125003-1-andriy.shevchenko@linux.intel.com> Cc: Andy Shevchenko Subject: [U-Boot] [PATCH v2 3/3] x86: Intel MID platforms has no microcode update X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" There is no microcode update available for SoCs used on Intel MID platforms. Use conditional to bypass it. Reviewed-by: Simon Glass Signed-off-by: Andy Shevchenko Reviewed-by: Bin Meng --- arch/x86/cpu/mp_init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/cpu/mp_init.c b/arch/x86/cpu/mp_init.c index 988073cc79..4e2f000f75 100644 --- a/arch/x86/cpu/mp_init.c +++ b/arch/x86/cpu/mp_init.c @@ -248,7 +248,7 @@ static int load_sipi_vector(atomic_t **ap_countp, int num_cpus) if (!stack) return -ENOMEM; params->stack_top = (u32)(stack + size); -#if !defined(CONFIG_QEMU) && !defined(CONFIG_HAVE_FSP) +#if !defined(CONFIG_QEMU) && !defined(CONFIG_HAVE_FSP) && !defined(CONFIG_INTEL_MID) params->microcode_ptr = ucode_base; debug("Microcode at %x\n", params->microcode_ptr); #endif