From patchwork Wed Feb 1 13:46:00 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Albert ARIBAUD (3ADEV)" X-Patchwork-Id: 722533 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3vD4Ct5gCVz9sDB for ; Thu, 2 Feb 2017 00:46:18 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id C84BB4B82E; Wed, 1 Feb 2017 14:46:16 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id CQ8mbCzlFxov; Wed, 1 Feb 2017 14:46:16 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id F0DBD4B709; Wed, 1 Feb 2017 14:46:15 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 5B5504B709 for ; Wed, 1 Feb 2017 14:46:13 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id tCfI0mG3Tcyr for ; Wed, 1 Feb 2017 14:46:13 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from smtp4-g21.free.fr (smtp4-g21.free.fr [212.27.42.4]) by theia.denx.de (Postfix) with ESMTPS id 1BE444B6AC for ; Wed, 1 Feb 2017 14:46:10 +0100 (CET) Received: from localhost.localdomain (unknown [82.64.3.181]) (Authenticated sender: aribaud.smtp) by smtp4-g21.free.fr (Postfix) with ESMTPSA id 06D4519F5C2; Wed, 1 Feb 2017 14:46:06 +0100 (CET) From: "Albert ARIBAUD (3ADEV)" To: u-boot@lists.denx.de Date: Wed, 1 Feb 2017 14:46:00 +0100 Message-Id: <20170201134600.2702-1-albert.aribaud@3adev.fr> X-Mailer: git-send-email 2.11.0 Cc: "Albert ARIBAUD \(3ADEV\)" Subject: [U-Boot] [PATCH] pcm052: fix DDR initialization sequence X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The sequence erroneously launched the DDR controller initialization before the pad muxing was done, causing DRAM size computation to hang. Configuring the pads first then launching DDR controller initialization prevents the DRAM hanging. Signed-off-by: Albert ARIBAUD (3ADEV) --- board/phytec/pcm052/pcm052.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/board/phytec/pcm052/pcm052.c b/board/phytec/pcm052/pcm052.c index e75ff4fc3a..54a4e4f9c3 100644 --- a/board/phytec/pcm052/pcm052.c +++ b/board/phytec/pcm052/pcm052.c @@ -258,8 +258,7 @@ int dram_init(void) .wldqsen = 25, }; - ddrmc_ctrl_init_ddr3(&pcm052_ddr_timings, pcm052_cr_settings, - pcm052_phy_settings, 1, 2); + const int row_diff = 2; #elif defined(CONFIG_TARGET_BK4R1) @@ -314,8 +313,7 @@ int dram_init(void) .wldqsen = 25, }; - ddrmc_ctrl_init_ddr3(&pcm052_ddr_timings, pcm052_cr_settings, - pcm052_phy_settings, 1, 1); + const int row_diff = 1; #else /* Unknown PCM052 variant */ @@ -325,6 +323,9 @@ int dram_init(void) imx_iomux_v3_setup_multiple_pads(pcm052_pads, ARRAY_SIZE(pcm052_pads)); + ddrmc_ctrl_init_ddr3(&pcm052_ddr_timings, pcm052_cr_settings, + pcm052_phy_settings, 1, row_diff); + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); return 0;