diff mbox

[U-Boot] sunxi: H3/A64: fix non-ODT setting

Message ID 20161228185049.15953-2-icenowy@aosc.xyz
State Superseded
Delegated to: Jagannadha Sutradharudu Teki
Headers show

Commit Message

Icenowy Zheng Dec. 28, 2016, 6:50 p.m. UTC 
From: Andre Przywara <andre.przywara@arm.com>

According to Jens disabling the on-die-termination should set bit 5,
not bit 1 in the respective register. Fix this.

Reported-by: Jens Kuske <jenskuske@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 arch/arm/mach-sunxi/dram_sun8i_h3.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Maxime Ripard Jan. 5, 2017, 10:15 p.m. UTC | #1 
On Thu, Dec 29, 2016 at 02:50:49AM +0800, Icenowy Zheng wrote:
> From: Andre Przywara <andre.przywara@arm.com>
> 
> According to Jens disabling the on-die-termination should set bit 5,
> not bit 1 in the respective register. Fix this.
> 
> Reported-by: Jens Kuske <jenskuske@gmail.com>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>

This has already been sent and merged (and it's missing your
Signed-off-by).

Maxime
diff mbox

Patch

diff --git a/arch/arm/mach-sunxi/dram_sun8i_h3.c b/arch/arm/mach-sunxi/dram_sun8i_h3.c
index b08b8e67cc..8e2527dee1 100644
--- a/arch/arm/mach-sunxi/dram_sun8i_h3.c
+++ b/arch/arm/mach-sunxi/dram_sun8i_h3.c
@@ -347,7 +347,7 @@  static int mctl_channel_init(struct dram_para *para)
 		clrsetbits_le32(&mctl_ctl->datx[i].gcr, (0x3 << 4) |
 				(0x1 << 1) | (0x3 << 2) | (0x3 << 12) |
 				(0x3 << 14),
-				IS_ENABLED(CONFIG_DRAM_ODT_EN) ? 0x0 : 0x2);
+				IS_ENABLED(CONFIG_DRAM_ODT_EN) ? 0x0 : 0x20);
 
 	/* AC PDR should always ON */
 	setbits_le32(&mctl_ctl->aciocr, 0x1 << 1);