From patchwork Tue Nov 22 17:13:31 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabien Parent X-Patchwork-Id: 697806 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3tNXBz4S8wz9t0H for ; Wed, 23 Nov 2016 04:14:35 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=baylibre-com.20150623.gappssmtp.com header.i=@baylibre-com.20150623.gappssmtp.com header.b="PMYbzxuV"; dkim-atps=neutral Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 1639AA7612; Tue, 22 Nov 2016 18:14:09 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Oowj0MV7Pyff; Tue, 22 Nov 2016 18:14:08 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 15CF3A75A9; Tue, 22 Nov 2016 18:13:56 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 799FAA7579 for ; Tue, 22 Nov 2016 18:13:47 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 0ChroaF6215G for ; Tue, 22 Nov 2016 18:13:47 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-wm0-f45.google.com (mail-wm0-f45.google.com [74.125.82.45]) by theia.denx.de (Postfix) with ESMTPS id 0500FA75A9 for ; Tue, 22 Nov 2016 18:13:38 +0100 (CET) Received: by mail-wm0-f45.google.com with SMTP id f82so36183628wmf.1 for ; Tue, 22 Nov 2016 09:13:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Bb2xsJ5FBLyCqb92BUNKYe+eMUTVa+0rgGDuTGW+Ln0=; b=PMYbzxuVhUa0U05J0QVjuYY/a2d2vDPgyBVDvAdHsB8EuvB5bz+iwMaSg1XsoflNu8 c45LoyIlGfJlSmvXYGYsgY3piUg+0aFw/BFBbBAiKNWMa11V765t++C4dd19NiDgDZFq owIEQvA5CSC0i7JlsZ3gymkGeK+ZS1vY727uwq6FD6n8F8R58sxLXQKWI4xF+dhc5NsM qAUtl9s4fXEBve5wBBszZ0K4QNeB927AAAhD/xhq9tE4lS+g1E3GkGYYAWBbh0wyy1Mz l3MTd3gGqdFMfwkKYxPE0A7AHVgmb/+Hu/QrxTCaHvoKCua4PmnW6D0AhVW6NAvEsaxX uuqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Bb2xsJ5FBLyCqb92BUNKYe+eMUTVa+0rgGDuTGW+Ln0=; b=X64DkJm2IEBDntR0nC38q7elN4fJ5/TwloUn/MI7SWbWk2W3DQIPd4PM7wcLjxxnx2 CqkusHaCuCGUGCJnpDfcbhnF96VRQfqHXh8VXZnaPXIfjRncfOB5zgAj0DBvjAbvjwfj ZjjitF7NvvC9PzVFpdrcI5BeKvm2WT+Oj8wA8ubZEXNg0FUzE0iqKZBsXshw4qGYJ9jp 0uYesIZFCaoVgz/61HX7OzF8x1lGabn8EU/CFiRznOcjNqr+E7usBKHKzDKvJh5gQvZ3 Uh40uvbmoSMfRb7AD1HC0B8RjgKNiFWbBH8CaNNzBraHw4uTe7z/i10ccceYs6pqQlLY Dcgw== X-Gm-Message-State: AKaTC00lI9GigOME7cbb5fVh44EDVBfTpcVCwY7PvTOoS+52w5+wcoJRbePV+kwBoRLLZkaF X-Received: by 10.194.231.8 with SMTP id tc8mr14840423wjc.193.1479834818156; Tue, 22 Nov 2016 09:13:38 -0800 (PST) Received: from localhost.localdomain ([90.63.244.31]) by smtp.gmail.com with ESMTPSA id j1sm31908898wjm.26.2016.11.22.09.13.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 22 Nov 2016 09:13:37 -0800 (PST) From: Fabien Parent To: u-boot@lists.denx.de Date: Tue, 22 Nov 2016 18:13:31 +0100 Message-Id: <20161122171333.30192-3-fparent@baylibre.com> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20161122171333.30192-1-fparent@baylibre.com> References: <20161122171333.30192-1-fparent@baylibre.com> Cc: Tom Rini Subject: [U-Boot] [PATCH v2 2/4] davinci: omapl138_lcdk: configure ddr2 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The SPL is unable to load u-boot because the DDR2 is not configured. Configure the DDR2. Signed-off-by: Fabien Parent --- V1 -> V2 * New patch --- include/configs/omapl138_lcdk.h | 42 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h index ce3a8f4..2cdf892 100644 --- a/include/configs/omapl138_lcdk.h +++ b/include/configs/omapl138_lcdk.h @@ -31,6 +31,7 @@ #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) #define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_DA850_PLL_INIT +#define CONFIG_SYS_DA850_DDR_INIT #define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_SYS_TEXT_BASE 0xc1080000 @@ -80,6 +81,47 @@ #define CONFIG_SYS_DA850_PLL1_PLLM 21 /* + * DDR2 memory configuration + */ +#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \ + DV_DDR_PHY_EXT_STRBEN | \ + (0x5 << DV_DDR_PHY_RD_LATENCY_SHIFT)) + +#define CONFIG_SYS_DA850_DDR2_SDBCR ( \ + (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \ + (1 << DV_DDR_SDCR_DDREN_SHIFT) | \ + (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \ + (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \ + (4 << DV_DDR_SDCR_CL_SHIFT) | \ + (3 << DV_DDR_SDCR_IBANK_SHIFT) | \ + (2 << DV_DDR_SDCR_PAGESIZE_SHIFT)) + +/* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */ +#define CONFIG_SYS_DA850_DDR2_SDBCR2 0 + +#define CONFIG_SYS_DA850_DDR2_SDTIMR ( \ + (19 << DV_DDR_SDTMR1_RFC_SHIFT) | \ + (1 << DV_DDR_SDTMR1_RP_SHIFT) | \ + (1 << DV_DDR_SDTMR1_RCD_SHIFT) | \ + (2 << DV_DDR_SDTMR1_WR_SHIFT) | \ + (6 << DV_DDR_SDTMR1_RAS_SHIFT) | \ + (8 << DV_DDR_SDTMR1_RC_SHIFT) | \ + (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \ + (1 << DV_DDR_SDTMR1_WTR_SHIFT)) + +#define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \ + (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \ + (2 << DV_DDR_SDTMR2_XP_SHIFT) | \ + (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \ + (10 << DV_DDR_SDTMR2_XSNR_SHIFT) | \ + (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \ + (1 << DV_DDR_SDTMR2_RTP_SHIFT) | \ + (2 << DV_DDR_SDTMR2_CKE_SHIFT)) + +#define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000492 +#define CONFIG_SYS_DA850_DDR2_PBBPR 0x30 + +/* * Serial Driver info */ #define CONFIG_SYS_NS16550_SERIAL