From patchwork Wed Nov 9 10:21:31 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen-Yu Tsai X-Patchwork-Id: 692702 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3tDNwV11Khz9vDW for ; Wed, 9 Nov 2016 22:18:50 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 1EE5C4BA35; Wed, 9 Nov 2016 12:18:38 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 3xrG1uyM0zlk; Wed, 9 Nov 2016 12:18:38 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id C0E4DA75AC; Wed, 9 Nov 2016 12:18:21 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 4DB464BA35 for ; Wed, 9 Nov 2016 12:18:12 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id W5Ss9iIbI_RR for ; Wed, 9 Nov 2016 12:18:12 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from wens.csie.org (mirror2.csie.ntu.edu.tw [140.112.30.76]) by theia.denx.de (Postfix) with ESMTPS id CD5744B99D for ; Wed, 9 Nov 2016 12:18:07 +0100 (CET) Received: by wens.csie.org (Postfix, from userid 1000) id A15235FA53; Wed, 9 Nov 2016 18:23:50 +0800 (CST) From: Chen-Yu Tsai To: Hans de Goede , u-boot@lists.denx.de Date: Wed, 9 Nov 2016 18:21:31 +0800 Message-Id: <20161109102136.13479-6-wens@csie.org> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20161109102136.13479-1-wens@csie.org> References: <20161109102136.13479-1-wens@csie.org> Subject: [U-Boot] [PATCH 05/10] sunxi: Add PRCM register definition for sun9i/A80 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The A80 has a different PRCM register layout. Signed-off-by: Chen-Yu Tsai Reviewed-by: Hans de Goede --- arch/arm/include/asm/arch-sunxi/prcm_sun9i.h | 55 ++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) create mode 100644 arch/arm/include/asm/arch-sunxi/prcm_sun9i.h diff --git a/arch/arm/include/asm/arch-sunxi/prcm_sun9i.h b/arch/arm/include/asm/arch-sunxi/prcm_sun9i.h new file mode 100644 index 000000000000..f4732335fbcc --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/prcm_sun9i.h @@ -0,0 +1,55 @@ +/* + * Sunxi A80 Power Reset and Clock Module register definition + * + * (C) Copyright 2016 Chen-Yu Tsai + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SUNXI_PRCM_SUN9I_H +#define _SUNXI_PRCM_SUN9I_H + +struct __packed sunxi_prcm_reg { + u32 cpus_rst; /* 0x000 */ + u32 cpu_rst[2]; /* 0x004 */ + u8 res0[0x4]; /* 0x00c */ + u32 cpus_cfg; /* 0x010 */ + u8 res1[0x8]; /* 0x014 */ + u32 apbs_ratio; /* 0x01c */ + u8 res2[0x8]; /* 0x020 */ + u32 apbs_gate; /* 0x028 */ + u8 res3[0x18]; /* 0x02c */ + u32 pll_ctrl1; /* 0x044 */ + u8 res4[0xc]; /* 0x048 */ + u32 clk_cir; /* 0x054 */ + u32 clk_i2s0; /* 0x058 */ + u32 clk_i2s1; /* 0x05c */ + u8 res5[0x50]; /* 0x060 */ + u32 apb0_reset; /* 0x0b0 */ + u8 res6[0x4c]; /* 0x0b4 */ + u32 cpu_pwroff[2]; /* 0x100 */ + u8 res7[0x8]; /* 0x108 */ + u32 vdd_sys_pwroff; /* 0x110 */ + u8 res8[0x4]; /* 0x114 */ + u32 gpu_pwroff; /* 0x118 */ + u8 res9[0x4]; /* 0x11c */ + u32 vdd_sys_rst; /* 0x120 */ + u8 res10[0x1c]; /* 0x124 */ + u32 cpu_pwr_clamp[2][4]; /* 0x140 */ + u32 super_standby_flag; /* 0x160 */ + u32 cpu_soft_entry; /* 0x164 */ + u32 super_standby_entry; /* 0x168 */ + u8 res11[0x34]; /* 0x16c */ + u32 nmi_irq_ctrl; /* 0x1a0 */ + u32 nmi_irq_en; /* 0x1a4 */ + u32 nmi_irq_status; /* 0x1a8 */ + u8 res12[0x14]; /* 0x1ac */ + u32 pll_audio_ctrl; /* 0x1c0 */ + u32 pll_audio_bias; /* 0x1c4 */ + u32 pll_audio_pat_cfg; /* 0x1c8 */ + u32 pll_audio_ctrl_sw; /* 0x1cc */ + u8 res13[0x20]; /* 0x1d0 */ + u32 osc24m_ctrl; /* 0x1f0 */ +}; + +#endif /* _SUNXI_PRCM_SUN9I_H */