From patchwork Wed Nov 9 10:21:28 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen-Yu Tsai X-Patchwork-Id: 692709 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3tDNyR4wqwz9vDW for ; Wed, 9 Nov 2016 22:20:31 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 48174A7622; Wed, 9 Nov 2016 12:19:12 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id kBXhgZgpBDGB; Wed, 9 Nov 2016 12:19:12 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id EE5C4A75C6; Wed, 9 Nov 2016 12:18:37 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 7B8264BA29 for ; Wed, 9 Nov 2016 12:18:16 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id lrl2I2xDxrKO for ; Wed, 9 Nov 2016 12:18:16 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from wens.csie.org (mirror2.csie.ntu.edu.tw [140.112.30.76]) by theia.denx.de (Postfix) with ESMTPS id D7117A7537 for ; Wed, 9 Nov 2016 12:18:14 +0100 (CET) Received: by wens.csie.org (Postfix, from userid 1000) id 925015FA00; Wed, 9 Nov 2016 18:23:50 +0800 (CST) From: Chen-Yu Tsai To: Hans de Goede , u-boot@lists.denx.de Date: Wed, 9 Nov 2016 18:21:28 +0800 Message-Id: <20161109102136.13479-3-wens@csie.org> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20161109102136.13479-1-wens@csie.org> References: <20161109102136.13479-1-wens@csie.org> Subject: [U-Boot] [PATCH 02/10] sunxi: Add CCI-400 and CPUCFG registers base address for sun9i/A80 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The A80, having 2 clusters of 4 cores each, has an ARM CCI-400 hardware block for cache coherency. Add the base address for CCI-400, and also add the base address for CPUCFG. Signed-off-by: Chen-Yu Tsai Reviewed-by: Hans de Goede --- arch/arm/include/asm/arch-sunxi/cpu_sun9i.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h index c775bcc515a0..88b48c644c06 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h @@ -17,6 +17,9 @@ #define REGS_APB1_BASE 0x07000000 #define REGS_RCPUS_BASE 0x08000000 +#define SUNXI_CPUCFG_BASE 0x01700000 +#define SUNXI_CCI400_BASE 0x01790000 + #define SUNXI_SRAM_D_BASE 0x08100000 /* AHB0 Module */