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[202.36.163.2]) by smtp.gmail.com with ESMTPSA id fm6sm22765824pab.37.2016.10.13.20.19.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 13 Oct 2016 20:19:22 -0700 (PDT) From: Chris Packham To: u-boot@lists.denx.de Date: Fri, 14 Oct 2016 16:19:12 +1300 Message-Id: <20161014031912.16913-1-judge.packham@gmail.com> X-Mailer: git-send-email 2.10.0.479.g7c56b16 Cc: Jagan Teki , Albert Aribaud , Stefan Roese , Chris Packham Subject: [U-Boot] [PATCH] spi: kirkwood_spi: implement mvebu_spi_set_mode() X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Set the appropriate bits in the interface config register based on the SPI_ mode flags. Signed-off-by: Chris Packham Reviewed-by: Stefan Roese --- arch/arm/include/asm/arch-mvebu/spi.h | 4 ++++ drivers/spi/kirkwood_spi.c | 13 +++++++++++++ 2 files changed, 17 insertions(+) diff --git a/arch/arm/include/asm/arch-mvebu/spi.h b/arch/arm/include/asm/arch-mvebu/spi.h index 78869a253d1f..3545aed17347 100644 --- a/arch/arm/include/asm/arch-mvebu/spi.h +++ b/arch/arm/include/asm/arch-mvebu/spi.h @@ -52,6 +52,10 @@ struct kwspi_registers { #define KWSPI_ADRLEN_3BYTE (2 << 8) #define KWSPI_ADRLEN_4BYTE (3 << 8) #define KWSPI_ADRLEN_MASK (3 << 8) +#define KWSPI_CPOL (1 << 11) +#define KWSPI_CPHA (1 << 12) +#define KWSPI_TXLSBF (1 << 13) +#define KWSPI_RXLSBF (1 << 14) #define KWSPI_IRQUNMASK 1 /* unmask SPI interrupt */ #define KWSPI_IRQMASK 0 /* mask SPI interrupt */ diff --git a/drivers/spi/kirkwood_spi.c b/drivers/spi/kirkwood_spi.c index 6851ba942f51..69a0be9ea5b2 100644 --- a/drivers/spi/kirkwood_spi.c +++ b/drivers/spi/kirkwood_spi.c @@ -271,6 +271,19 @@ static int mvebu_spi_set_speed(struct udevice *bus, uint hz) static int mvebu_spi_set_mode(struct udevice *bus, uint mode) { + struct mvebu_spi_platdata *plat = dev_get_platdata(bus); + struct kwspi_registers *reg = plat->spireg; + u32 data = readl(®->cfg); + + if (mode & SPI_CPHA) + data |= KWSPI_CPHA; + if (mode & SPI_CPOL) + data |= KWSPI_CPOL; + if (mode & SPI_LSB_FIRST) + data |= (KWSPI_RXLSBF | KWSPI_TXLSBF); + + writel(data, ®->cfg); + return 0; }