From patchwork Mon Oct 10 15:50:55 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephen Warren X-Patchwork-Id: 680465 X-Patchwork-Delegate: twarren@nvidia.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3st4Nk3vBFz9ryn for ; Tue, 11 Oct 2016 02:51:18 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id ACC634B71E; Mon, 10 Oct 2016 17:51:15 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 5nprNkk8nP0Z; Mon, 10 Oct 2016 17:51:15 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 153154B660; Mon, 10 Oct 2016 17:51:15 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 61A1A4B660 for ; Mon, 10 Oct 2016 17:51:12 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id VMUjqUUQvPx7 for ; Mon, 10 Oct 2016 17:51:12 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from avon.wwwdotorg.org (avon.wwwdotorg.org [70.85.31.133]) by theia.denx.de (Postfix) with ESMTPS id 0D7914A039 for ; Mon, 10 Oct 2016 17:51:08 +0200 (CEST) Received: from swarren-lx1.nvidia.com (thunderhill.nvidia.com [216.228.112.22]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) by avon.wwwdotorg.org (Postfix) with ESMTPSA id 1CB931C03B4; Mon, 10 Oct 2016 09:51:05 -0600 (MDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.99.2 at avon.wwwdotorg.org From: Stephen Warren To: u-boot@lists.denx.de, Simon Glass , Tom Warren , Stephen Warren Date: Mon, 10 Oct 2016 09:50:55 -0600 Message-Id: <20161010155055.11543-1-swarren@wwwdotorg.org> X-Mailer: git-send-email 2.10.1 X-NVConfidentiality: public Subject: [U-Boot] [PATCH] ARM: tegra: reduce DRAM size mapped into MMU on ARM64 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Stephen Warren ARM CPUs can architecturally (speculatively) prefetch completely arbitrary normal memory locations, as defined by the current translation tables. The current MMU configuration for 64-bit Tegras maps an extremely large range of addresses as DRAM, well beyond the actual physical maximum DRAM window, even though U-Boot only needs access to the first 2GB of DRAM; the Tegra port of U-Boot deliberately limits itself to 2GB of RAM since some HW modules on at least some 64-bit Tegra SoCs can only access a 32-bit physical address space. This change reduces the amount of RAM mapped via the MMU to disallow the CPU from ever speculatively accessing RAM that U-Boot will definitely not access. This avoids the possibility of the HW raising SError due to accesses to always-invalid physical addresses. Signed-off-by: Stephen Warren --- arch/arm/mach-tegra/arm64-mmu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-tegra/arm64-mmu.c b/arch/arm/mach-tegra/arm64-mmu.c index 7b1d258ed84f..a79a5192e076 100644 --- a/arch/arm/mach-tegra/arm64-mmu.c +++ b/arch/arm/mach-tegra/arm64-mmu.c @@ -23,7 +23,7 @@ static struct mm_region tegra_mem_map[] = { }, { .virt = 0x80000000UL, .phys = 0x80000000UL, - .size = 0xff80000000UL, + .size = 0x80000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE }, {