From patchwork Fri Sep 16 13:07:53 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Roese X-Patchwork-Id: 670853 X-Patchwork-Delegate: hs@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3sbFwZ0m2Lz9rxv for ; Fri, 16 Sep 2016 23:09:02 +1000 (AEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 0BB694B98A; Fri, 16 Sep 2016 15:08:37 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id bELdUVVB7Ob1; Fri, 16 Sep 2016 15:08:36 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id CDE19A757A; Fri, 16 Sep 2016 15:08:24 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id E1F664BA5C for ; Fri, 16 Sep 2016 15:08:14 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id pIBQgh38QgC8 for ; Fri, 16 Sep 2016 15:08:14 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mx1.mailbox.org (mx1.mailbox.org [80.241.60.212]) by theia.denx.de (Postfix) with ESMTPS id 3AAC24BF90 for ; Fri, 16 Sep 2016 15:08:11 +0200 (CEST) Received: from smtp1.mailbox.org (smtp1.mailbox.org [80.241.60.240]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.mailbox.org (Postfix) with ESMTPS id 26AA0440B2; Fri, 16 Sep 2016 15:08:11 +0200 (CEST) X-Virus-Scanned: amavisd-new at heinlein-support.de Received: from smtp1.mailbox.org ([80.241.60.240]) by gerste.heinlein-support.de (gerste.heinlein-support.de [91.198.250.173]) (amavisd-new, port 10030) with ESMTP id 2HbBk4hOBJzq; Fri, 16 Sep 2016 15:07:59 +0200 (CEST) From: Stefan Roese To: u-boot@lists.denx.de Date: Fri, 16 Sep 2016 15:07:53 +0200 Message-Id: <20160916130755.9883-5-sr@denx.de> In-Reply-To: <20160916130755.9883-1-sr@denx.de> References: <20160916130755.9883-1-sr@denx.de> Cc: Hua Jing , Haim Boot , Hanna Hawa , Nadav Haklai , Victor Gu , Kostya Porotchkin , Terry Zhou , Wilson Ding Subject: [U-Boot] [PATCH 5/7] i2c: mv_i2c.c: Enable runtime speed selection (standard vs fast mode) X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This patch adds runtime speed configuration to the mv_i2c driver. Currently standard (max 100kHz) and fast mode (max 400kHz) are supported. Signed-off-by: Stefan Roese Cc: Nadav Haklai Cc: Kostya Porotchkin Cc: Wilson Ding Cc: Victor Gu Cc: Hua Jing Cc: Terry Zhou Cc: Hanna Hawa Cc: Haim Boot Cc: Heiko Schocher --- drivers/i2c/mv_i2c.c | 30 +++++++++++++++++++++++++++++- drivers/i2c/mv_i2c.h | 15 +++++++++------ 2 files changed, 38 insertions(+), 7 deletions(-) diff --git a/drivers/i2c/mv_i2c.c b/drivers/i2c/mv_i2c.c index 341126a..291b2d7 100644 --- a/drivers/i2c/mv_i2c.c +++ b/drivers/i2c/mv_i2c.c @@ -68,6 +68,10 @@ __weak void i2c_clk_enable(void) */ static void i2c_reset(struct mv_i2c *base) { + u32 icr_mode; + + /* Save bus mode (standard or fast speed) for later use */ + icr_mode = readl(&base->icr) & ICR_MODE_MASK; writel(readl(&base->icr) & ~ICR_IUE, &base->icr); /* disable unit */ writel(readl(&base->icr) | ICR_UR, &base->icr); /* reset the unit */ udelay(100); @@ -76,7 +80,8 @@ static void i2c_reset(struct mv_i2c *base) i2c_clk_enable(); writel(CONFIG_SYS_I2C_SLAVE, &base->isar); /* set our slave address */ - writel(I2C_ICR_INIT, &base->icr); /* set control reg values */ + /* set control reg values */ + writel(I2C_ICR_INIT | icr_mode, &base->icr); writel(I2C_ISR_INIT, &base->isr); /* set clear interrupt bits */ writel(readl(&base->icr) | ICR_IUE, &base->icr); /* enable unit */ udelay(100); @@ -416,6 +421,8 @@ unsigned int i2c_get_bus_num(void) /* API Functions */ void i2c_init(int speed, int slaveaddr) { + u32 val; + #ifdef CONFIG_I2C_MULTI_BUS current_bus = 0; base_glob = (struct mv_i2c *)i2c_regs[current_bus]; @@ -423,6 +430,12 @@ void i2c_init(int speed, int slaveaddr) base_glob = (struct mv_i2c *)CONFIG_MV_I2C_REG; #endif + if (speed > 100000) + val = ICR_FM; + else + val = ICR_SM; + clrsetbits_le32(&base_glob->icr, ICR_MODE_MASK, val); + i2c_board_init(base_glob); } @@ -543,6 +556,20 @@ static int mv_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs) omsg->len, dmsg->buf, dmsg->len); } +static int mv_i2c_set_bus_speed(struct udevice *bus, unsigned int speed) +{ + struct mv_i2c_priv *priv = dev_get_priv(bus); + u32 val; + + if (speed > 100000) + val = ICR_FM; + else + val = ICR_SM; + clrsetbits_le32(&priv->base->icr, ICR_MODE_MASK, val); + + return 0; +} + static int mv_i2c_probe(struct udevice *bus) { struct mv_i2c_priv *priv = dev_get_priv(bus); @@ -554,6 +581,7 @@ static int mv_i2c_probe(struct udevice *bus) static const struct dm_i2c_ops mv_i2c_ops = { .xfer = mv_i2c_xfer, + .set_bus_speed = mv_i2c_set_bus_speed, }; static const struct udevice_id mv_i2c_ids[] = { diff --git a/drivers/i2c/mv_i2c.h b/drivers/i2c/mv_i2c.h index ae27c44..1e62892 100644 --- a/drivers/i2c/mv_i2c.h +++ b/drivers/i2c/mv_i2c.h @@ -23,12 +23,7 @@ extern void i2c_clk_enable(void); #define I2C_READ 0 #define I2C_WRITE 1 -#if (CONFIG_SYS_I2C_SPEED == 400000) -#define I2C_ICR_INIT (ICR_FM | ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD \ - | ICR_SCLE) -#else #define I2C_ICR_INIT (ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE) -#endif #define I2C_ISR_INIT 0x7FF /* ----- Control register bits ---------------------------------------- */ @@ -48,7 +43,15 @@ extern void i2c_clk_enable(void); #define ICR_ALDIE 0x1000 /* enable arbitration interrupt */ #define ICR_SADIE 0x2000 /* slave address detected int enable */ #define ICR_UR 0x4000 /* unit reset */ -#define ICR_FM 0x8000 /* Fast Mode */ +#ifdef CONFIG_ARMADA_3700 +#define ICR_SM 0x00000 /* Standard Mode */ +#define ICR_FM 0x10000 /* Fast Mode */ +#define ICR_MODE_MASK 0x30000 /* Mode mask */ +#else +#define ICR_SM 0x00000 /* Standard Mode */ +#define ICR_FM 0x08000 /* Fast Mode */ +#define ICR_MODE_MASK 0x18000 /* Mode mask */ +#endif /* ----- Status register bits ----------------------------------------- */