From patchwork Wed Jul 27 21:24:51 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephen Warren X-Patchwork-Id: 653481 X-Patchwork-Delegate: twarren@nvidia.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3s07M53Jpxz9sBM for ; Thu, 28 Jul 2016 07:25:36 +1000 (AEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 546C6A755D; Wed, 27 Jul 2016 23:25:31 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id RDOAMJJYrGVB; Wed, 27 Jul 2016 23:25:31 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id E4ABFA7534; Wed, 27 Jul 2016 23:25:30 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id E8B9DA7550 for ; Wed, 27 Jul 2016 23:25:27 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id WDWKLBr6bGGA for ; Wed, 27 Jul 2016 23:25:27 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from avon.wwwdotorg.org (avon.wwwdotorg.org [70.85.31.133]) by theia.denx.de (Postfix) with ESMTPS id 7EB52A7524 for ; Wed, 27 Jul 2016 23:25:25 +0200 (CEST) Received: from swarren-lx1.nvidia.com (thunderhill.nvidia.com [216.228.112.22]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) by avon.wwwdotorg.org (Postfix) with ESMTPSA id 1B6291C047A; Wed, 27 Jul 2016 15:25:26 -0600 (MDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.99 at avon.wwwdotorg.org From: Stephen Warren To: u-boot@lists.denx.de, Simon Glass , Tom Warren , Stephen Warren Date: Wed, 27 Jul 2016 15:24:51 -0600 Message-Id: <20160727212457.20038-3-swarren@wwwdotorg.org> X-Mailer: git-send-email 2.9.2 In-Reply-To: <20160727212457.20038-1-swarren@wwwdotorg.org> References: <20160727212457.20038-1-swarren@wwwdotorg.org> X-NVConfidentiality: public Subject: [U-Boot] [PATCH 3/9] ARM: tegra: add BPMP and dependencies to Tegra186 DT X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Stephen Warren This adds the DT content that's needed to allow board DTs to enable use of BPMP, clocks, resets, GPIOs, eMMC, and SD cards. Signed-off-by: Stephen Warren Reviewed-by: Simon Glass --- arch/arm/dts/tegra186.dtsi | 55 ++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 53 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/tegra186.dtsi b/arch/arm/dts/tegra186.dtsi index 650feb60b1ab..25e1e8dfc035 100644 --- a/arch/arm/dts/tegra186.dtsi +++ b/arch/arm/dts/tegra186.dtsi @@ -1,14 +1,16 @@ #include "skeleton.dtsi" +#include #include #include #include +#include / { compatible = "nvidia,tegra186"; #address-cells = <2>; #size-cells = <2>; - gpio@2200000 { + gpio_main: gpio@2200000 { compatible = "nvidia,tegra186-gpio"; reg-names = "security", "gpio"; reg = @@ -34,9 +36,24 @@ status = "disabled"; }; + sdhci@3400000 { + compatible = "nvidia,tegra186-sdhci"; + reg = <0x0 0x03400000 0x0 0x200>; + resets = <&bpmp TEGRA186_RESET_SDMMC1>; + reset-names = "sdmmc"; + clocks = <&bpmp TEGRA186_CLK_SDMMC1>; + clock-names = "sdmmc"; + interrupts = ; + status = "disabled"; + }; + sdhci@3460000 { compatible = "nvidia,tegra186-sdhci"; reg = <0x0 0x03460000 0x0 0x200>; + resets = <&bpmp TEGRA186_RESET_SDMMC4>; + reset-names = "sdmmc"; + clocks = <&bpmp TEGRA186_CLK_SDMMC4>; + clock-names = "sdmmc"; interrupts = ; status = "disabled"; }; @@ -49,7 +66,7 @@ #mbox-cells = <2>; }; - gpio@c2f0000 { + gpio_aon: gpio@c2f0000 { compatible = "nvidia,tegra186-gpio-aon"; reg-names = "security", "gpio"; reg = @@ -62,4 +79,38 @@ interrupt-controller; #interrupt-cells = <2>; }; + + sysram@30000000 { + compatible = "nvidia,tegra186-sysram", "mmio-sram"; + reg = <0x0 0x30000000 0x0 0x50000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>; + + sysram_cpu_bpmp_tx: shmem@4e000 { + compatible = "nvidia,tegra186-bpmp-shmem"; + reg = <0x0 0x4e000 0x0 0x1000>; + }; + + sysram_cpu_bpmp_rx: shmem@4f000 { + compatible = "nvidia,tegra186-bpmp-shmem"; + reg = <0x0 0x4f000 0x0 0x1000>; + }; + }; + + bpmp: bpmp { + compatible = "nvidia,tegra186-bpmp"; + mboxes = <&hsp HSP_MBOX_TYPE_DB HSP_DB_MASTER_BPMP>; + /* + * In theory, these references, and the configuration in the + * node these reference point at, are board-specific, since + * they depend on the BCT's memory carve-out setup, the + * firmware that's actually loaded onto the BPMP, etc. However, + * in practice, all boards are likely to use identical values. + */ + shmem = <&sysram_cpu_bpmp_tx &sysram_cpu_bpmp_rx>; + #clock-cells = <1>; + #power-domain-cells = <1>; + #reset-cells = <1>; + }; };