diff mbox

[U-Boot] fixing typo error in README file. CPU15 -> CP15

Message ID 20160720135612.GA6113@gmail.com
State Accepted
Delegated to: Tom Rini
Headers show

Commit Message

yeongjun Kim July 20, 2016, 1:56 p.m. UTC
It looks typo error. 
Not CPU15, CP15(CoProcessor15)
	
Signed-off-by: yeongjun Kim <iam.yeongjunkim@gmail.com>
---
 README | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Jaehoon Chung July 21, 2016, 1:34 p.m. UTC | #1
Hi Yeongjun,

On 07/20/2016 10:56 PM, yeongjun Kim wrote:
> It looks typo error. 

It's not error..Just typo.
Subject should be add the prefix "README: fix the typo..."

> Not CPU15, CP15(CoProcessor15)
> 	
> Signed-off-by: yeongjun Kim <iam.yeongjunkim@gmail.com>
> ---

If you send the patch V2, add the changelog at here.
Write the changelog what is changed from previous patch.

But you're right, it's typo. 
I added the Simon as Author who sent patch.

Best Regards,
Jaehoon Chung

>  README | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/README b/README
> index 3c3b699..8887cf5 100644
> --- a/README
> +++ b/README
> @@ -4806,7 +4806,7 @@ Low Level (hardware related) configuration options:
>  
>  - CONFIG_SKIP_LOWLEVEL_INIT_ONLY
>  		[ARM926EJ-S only] This allows just the call to lowlevel_init()
> -		to be skipped. The normal CPU15 init (such as enabling the
> +		to be skipped. The normal CP15 init (such as enabling the
>  		instruction cache) is still performed.
>  
>  - CONFIG_SPL_BUILD
>
Tom Rini July 23, 2016, 12:13 a.m. UTC | #2
On Wed, Jul 20, 2016 at 10:56:12PM +0900, yeongjun Kim wrote:

> It looks typo error. 
> Not CPU15, CP15(CoProcessor15)
> 	
> Signed-off-by: yeongjun Kim <iam.yeongjunkim@gmail.com>

Applied to u-boot/master, thanks!
diff mbox

Patch

diff --git a/README b/README
index 3c3b699..8887cf5 100644
--- a/README
+++ b/README
@@ -4806,7 +4806,7 @@  Low Level (hardware related) configuration options:
 
 - CONFIG_SKIP_LOWLEVEL_INIT_ONLY
 		[ARM926EJ-S only] This allows just the call to lowlevel_init()
-		to be skipped. The normal CPU15 init (such as enabling the
+		to be skipped. The normal CP15 init (such as enabling the
 		instruction cache) is still performed.
 
 - CONFIG_SPL_BUILD