From patchwork Thu Jun 9 12:09:52 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Burton X-Patchwork-Id: 632734 X-Patchwork-Delegate: daniel.schwierzeck@googlemail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3rQPJh2qBrz9sdm for ; Thu, 9 Jun 2016 22:10:28 +1000 (AEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 50779A757A; Thu, 9 Jun 2016 14:10:26 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id BEemO9onZRY5; Thu, 9 Jun 2016 14:10:26 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 9FEAFA7517; Thu, 9 Jun 2016 14:10:25 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A0C36A7517 for ; Thu, 9 Jun 2016 14:10:23 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id O8GhrYxvS4Aw for ; Thu, 9 Jun 2016 14:10:23 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mailapp01.imgtec.com (mailapp01.imgtec.com [195.59.15.196]) by theia.denx.de (Postfix) with ESMTP id 121E2A74EE for ; Thu, 9 Jun 2016 14:10:23 +0200 (CEST) Received: from hhmail02.hh.imgtec.org (unknown [10.100.10.20]) by Forcepoint Email with ESMTPS id 5A561F4623597; Thu, 9 Jun 2016 13:10:19 +0100 (IST) Received: from LEMAIL01.le.imgtec.org (192.168.152.62) by hhmail02.hh.imgtec.org (10.100.10.20) with Microsoft SMTP Server (TLS) id 14.3.294.0; Thu, 9 Jun 2016 13:10:22 +0100 Received: from localhost (10.100.200.166) by LEMAIL01.le.imgtec.org (192.168.152.62) with Microsoft SMTP Server (TLS) id 14.3.266.1; Thu, 9 Jun 2016 13:10:21 +0100 From: Paul Burton To: , Daniel Schwierzeck Date: Thu, 9 Jun 2016 13:09:52 +0100 Message-ID: <20160609120952.4799-2-paul.burton@imgtec.com> X-Mailer: git-send-email 2.8.3 In-Reply-To: <20160609120952.4799-1-paul.burton@imgtec.com> References: <20160609120952.4799-1-paul.burton@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [10.100.200.166] Subject: [U-Boot] [PATCH 2/2] MIPS: Make CONFIG_SYS_DCACHE_LINE_SIZE int, not hex X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" For consistency with the other cache-related Kconfig entries & the values actually set by boards, make CONFIG_SYS_DCACHE_LINE_SIZE an int entry instead of a hex entry. Signed-off-by: Paul Burton Fixes: 372286217f05 ("MIPS: Split I & D cache line size config") --- arch/mips/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 5c30ae9..21066f0 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -253,7 +253,7 @@ config SYS_DCACHE_SIZE The total size of the L1 Dcache, if known at compile time. config SYS_DCACHE_LINE_SIZE - hex + int default 0 help The size of L1 Dcache lines, if known at compile time.