[U-Boot,v4] x86: baytrail: Configure FSP UPD from device tree

Hi Simon,

On 08/11 08:06, Simon Glass wrote:
> Hi Andrew,
> 
> On 11 August 2015 at 06:08, Andrew Bradford <andrew@bradfordembedded.com> wrote:
> > Hi Simon,
> >
> > On 08/10 21:07, Simon Glass wrote:
> >> Hi Bin,
> >>
> >> On 10 August 2015 at 20:53, Bin Meng <bmeng.cn@gmail.com> wrote:
> >> > Hi Andrew,
> >> >
> >> > On Mon, Aug 10, 2015 at 7:32 PM, Andrew Bradford
> >> > <andrew@bradfordembedded.com> wrote:
> >> >> Hi Bin,
> >> >>
> >> >> On 08/09 10:52, Bin Meng wrote:
> >> >>> Hi Andrew,
> >> >>>
> >> >>> On Sun, Aug 9, 2015 at 9:08 AM, Andrew Bradford
> >> >>> <andrew@bradfordembedded.com> wrote:
> >> >>> > Hi Simon,
> >> >>> >
> >> >>> > On 08/08 10:18, Simon Glass wrote:
> >> >>> >> Hi,
> >> >>> >>
> >> >>> >> On 7 August 2015 at 06:44, Bin Meng <bmeng.cn@gmail.com> wrote:
> >> >>> >> > On Fri, Aug 7, 2015 at 8:36 PM, Andrew Bradford
> >> >>> >> > <andrew@bradfordembedded.com> wrote:
> >> >>> >> >> From: Andrew Bradford <andrew.bradford@kodakalaris.com>
> >> >>> >> >>
> >> >>> >> >> Allow for configuration of FSP UPD from the device tree which will
> >> >>> >> >> override any settings which the FSP was built with itself.
> >> >>> >> >>
> >> >>> >> >> Modify the MinnowMax and BayleyBay boards to transfer sensible UPD
> >> >>> >> >> settings from the Intel FSPv4 Gold release to the respective dts files,
> >> >>> >> >> with the condition that the memory-down parameters for MinnowMax are
> >> >>> >> >> also used.
> >> >>> >> >>
> >> >>> >> >> Signed-off-by: Andrew Bradford <andrew.bradford@kodakalaris.com>
> >> >>> >> >> ---
> >> >>> >> >>
> >> >>> >> >
> >> >>> >> > Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> >> >>> >> > Tested-by: Bin Meng <bmeng.cn@gmail.com>
> >> >>> >> >
> >> >>> >>
> >> >>> >> Acked-by: Simon Glass <sjg@chromium.org>
> >> >>> >> Tested on minnowmax:
> >> >>> >> Tested-by: Simon Glass <sjg@chromium.org>
> >> >>> >>
> >> >>> >> I found that I need to remove two properties from the minnowmax.dts:
> >> >>> >>
> >> >>> >> - fsp,enable-xhci needs to be removed as this does not work in U-Boot
> >> >>> >> at present and stops EHCI from working
> >> >>> >> - fsp,mrc-debug-msg needs to be removed to prevent debug information
> >> >>> >> being displayed
> >> >>> >>
> >> >>> >> I plan to apply this with these changes - please let me know if this
> >> >>> >> doesn't suit.
> >> >>> >
> >> >>> > I'm OK with disabling xhci and the MRC debug output in the FSP.
> >> >>> >
> >> >>> > But if xhci is disabled then I believe when Linux boots that the USB 3.0
> >> >>> > port on Minnow Max will only act as a USB 2.0 port.  That u-boot doesn't
> >> >>> > yet have working XHCI on E3800 means there is a tradeoff and I wasn't
> >> >>> > sure which was a better choice.
> >> >>>
> >> >>> Does these xHCI ports on MinnowMax work fully on Linux kernel? If it
> >> >>> works, I'd rather we keep fsp,enable-xhci in the U-Boot.
> >> >>
> >> >> I believe that the xhci port does work on Minnow Max in Linux but I do
> >> >> not have a board so I'm unable to test, sorry.
> >> >>
> >> >
> >> > OK, my test shows that ehci works fine in U-Boot on Bayley Bay.
> >> >
> >> > Hi Simon,
> >> >
> >> > What do you think regarding to xhci vs. ehci in U-Boot?
> >>
> >> The problem is that USB is then broken in U-Boot. I think it is better
> >> to limit the speed for the moment until we have that fixed. It is
> >> quite useful to be able to use a keyboard or USB stick in U-Boot.
> >>
> >> With my testing the bottom (blue) port works fine but the top port
> >> does not. This happens regardless of the xhci setting.
> >
> > Minnowmax has a USB power switch enable which determines if the VBUS2
> > net is turned on or not, which will supply or not supply power to the
> > USB 2.0 port.  The blue USB 3.0 port also has an enable.  Both enables
> > and the USB ports themselves are located on page 16 of the schematic
> > that I have.
> >
> > The switches to enable the VBUS for each port are active high and pulled
> > down.  So to turn them on, I believe that's the point of the pinmuxing
> > and GPIO settings which are used in the minnowmax.dts.  Can you verify
> > if these are correctly turning on VBUS2 (since it sounds like they are
> > turning on VBUS1)?  If not, when you turn these GPIO on manually, does
> > the USB 2.0 port work correctly?
> 
> I see power on the bottom port but not the top one.

OK, that's odd, but likely can be fixed with changes to the pin mux and
pad settings in the dts.  I believe that the "pad-offset" for
pin_usb_host_en1@0 is wrong and that it should be 0x250 instead of
0x258.


Does that fix it?

Thanks,
Andrew

+Gabriel

Hi Andrew,

On 11 August 2015 at 09:20, Andrew Bradford <andrew@bradfordembedded.com> wrote:
> Hi Simon,
>
> On 08/11 08:06, Simon Glass wrote:
>> Hi Andrew,
>>
>> On 11 August 2015 at 06:08, Andrew Bradford <andrew@bradfordembedded.com> wrote:
>> > Hi Simon,
>> >
>> > On 08/10 21:07, Simon Glass wrote:
>> >> Hi Bin,
>> >>
>> >> On 10 August 2015 at 20:53, Bin Meng <bmeng.cn@gmail.com> wrote:
>> >> > Hi Andrew,
>> >> >
>> >> > On Mon, Aug 10, 2015 at 7:32 PM, Andrew Bradford
>> >> > <andrew@bradfordembedded.com> wrote:
>> >> >> Hi Bin,
>> >> >>
>> >> >> On 08/09 10:52, Bin Meng wrote:
>> >> >>> Hi Andrew,
>> >> >>>
>> >> >>> On Sun, Aug 9, 2015 at 9:08 AM, Andrew Bradford
>> >> >>> <andrew@bradfordembedded.com> wrote:
>> >> >>> > Hi Simon,
>> >> >>> >
>> >> >>> > On 08/08 10:18, Simon Glass wrote:
>> >> >>> >> Hi,
>> >> >>> >>
>> >> >>> >> On 7 August 2015 at 06:44, Bin Meng <bmeng.cn@gmail.com> wrote:
>> >> >>> >> > On Fri, Aug 7, 2015 at 8:36 PM, Andrew Bradford
>> >> >>> >> > <andrew@bradfordembedded.com> wrote:
>> >> >>> >> >> From: Andrew Bradford <andrew.bradford@kodakalaris.com>
>> >> >>> >> >>
>> >> >>> >> >> Allow for configuration of FSP UPD from the device tree which will
>> >> >>> >> >> override any settings which the FSP was built with itself.
>> >> >>> >> >>
>> >> >>> >> >> Modify the MinnowMax and BayleyBay boards to transfer sensible UPD
>> >> >>> >> >> settings from the Intel FSPv4 Gold release to the respective dts files,
>> >> >>> >> >> with the condition that the memory-down parameters for MinnowMax are
>> >> >>> >> >> also used.
>> >> >>> >> >>
>> >> >>> >> >> Signed-off-by: Andrew Bradford <andrew.bradford@kodakalaris.com>
>> >> >>> >> >> ---
>> >> >>> >> >>
>> >> >>> >> >
>> >> >>> >> > Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
>> >> >>> >> > Tested-by: Bin Meng <bmeng.cn@gmail.com>
>> >> >>> >> >
>> >> >>> >>
>> >> >>> >> Acked-by: Simon Glass <sjg@chromium.org>
>> >> >>> >> Tested on minnowmax:
>> >> >>> >> Tested-by: Simon Glass <sjg@chromium.org>
>> >> >>> >>
>> >> >>> >> I found that I need to remove two properties from the minnowmax.dts:
>> >> >>> >>
>> >> >>> >> - fsp,enable-xhci needs to be removed as this does not work in U-Boot
>> >> >>> >> at present and stops EHCI from working
>> >> >>> >> - fsp,mrc-debug-msg needs to be removed to prevent debug information
>> >> >>> >> being displayed
>> >> >>> >>
>> >> >>> >> I plan to apply this with these changes - please let me know if this
>> >> >>> >> doesn't suit.
>> >> >>> >
>> >> >>> > I'm OK with disabling xhci and the MRC debug output in the FSP.
>> >> >>> >
>> >> >>> > But if xhci is disabled then I believe when Linux boots that the USB 3.0
>> >> >>> > port on Minnow Max will only act as a USB 2.0 port.  That u-boot doesn't
>> >> >>> > yet have working XHCI on E3800 means there is a tradeoff and I wasn't
>> >> >>> > sure which was a better choice.
>> >> >>>
>> >> >>> Does these xHCI ports on MinnowMax work fully on Linux kernel? If it
>> >> >>> works, I'd rather we keep fsp,enable-xhci in the U-Boot.
>> >> >>
>> >> >> I believe that the xhci port does work on Minnow Max in Linux but I do
>> >> >> not have a board so I'm unable to test, sorry.
>> >> >>
>> >> >
>> >> > OK, my test shows that ehci works fine in U-Boot on Bayley Bay.
>> >> >
>> >> > Hi Simon,
>> >> >
>> >> > What do you think regarding to xhci vs. ehci in U-Boot?
>> >>
>> >> The problem is that USB is then broken in U-Boot. I think it is better
>> >> to limit the speed for the moment until we have that fixed. It is
>> >> quite useful to be able to use a keyboard or USB stick in U-Boot.
>> >>
>> >> With my testing the bottom (blue) port works fine but the top port
>> >> does not. This happens regardless of the xhci setting.
>> >
>> > Minnowmax has a USB power switch enable which determines if the VBUS2
>> > net is turned on or not, which will supply or not supply power to the
>> > USB 2.0 port.  The blue USB 3.0 port also has an enable.  Both enables
>> > and the USB ports themselves are located on page 16 of the schematic
>> > that I have.
>> >
>> > The switches to enable the VBUS for each port are active high and pulled
>> > down.  So to turn them on, I believe that's the point of the pinmuxing
>> > and GPIO settings which are used in the minnowmax.dts.  Can you verify
>> > if these are correctly turning on VBUS2 (since it sounds like they are
>> > turning on VBUS1)?  If not, when you turn these GPIO on manually, does
>> > the USB 2.0 port work correctly?
>>
>> I see power on the bottom port but not the top one.
>
> OK, that's odd, but likely can be fixed with changes to the pin mux and
> pad settings in the dts.  I believe that the "pad-offset" for
> pin_usb_host_en1@0 is wrong and that it should be 0x250 instead of
> 0x258.
>
> diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
> index d0c0fe6..4988163 100644
> --- a/arch/x86/dts/minnowmax.dts
> +++ b/arch/x86/dts/minnowmax.dts
> @@ -39,7 +39,7 @@
>
>                 pin_usb_host_en1@0 {
>                         gpio-offset = <0x80 9>;
> -                       pad-offset = <0x258>;
> +                       pad-offset = <0x250>;
>                         mode-gpio;
>                         output-value = <1>;
>                         direction = <PIN_OUTPUT>;
>
> Does that fix it?

I dug into this a bit and it all seems quite broken:

- PCI bus configuration does not work in gpio_ich6_pinctrl_init(). I
will send a patch for this
- gpio_ich6_get_base() returns a 16-bit word but function is also used
to read the memory address which holds a 32-bit word
- Intel's hardware won't let you read the status of an output!

The last point means that _gpio_ich6_pinctrl_cfg_pin cannot work. We
need to mirror the lvl register in order to be able to read it.

I confirmed that with the 'correct' value in the lvl registers both
USB ports work.

Regards,
Simon

Hi Simon,

On 08/11 21:54, Simon Glass wrote:
> +Gabriel
> 
> Hi Andrew,
> 
> On 11 August 2015 at 09:20, Andrew Bradford <andrew@bradfordembedded.com> wrote:
> > Hi Simon,
> >
> > On 08/11 08:06, Simon Glass wrote:
> >> Hi Andrew,
> >>
> >> On 11 August 2015 at 06:08, Andrew Bradford <andrew@bradfordembedded.com> wrote:
> >> > Hi Simon,
> >> >
> >> > On 08/10 21:07, Simon Glass wrote:
> >> >> Hi Bin,
> >> >>
> >> >> On 10 August 2015 at 20:53, Bin Meng <bmeng.cn@gmail.com> wrote:
> >> >> > Hi Andrew,
> >> >> >
> >> >> > On Mon, Aug 10, 2015 at 7:32 PM, Andrew Bradford
> >> >> > <andrew@bradfordembedded.com> wrote:
> >> >> >> Hi Bin,
> >> >> >>
> >> >> >> On 08/09 10:52, Bin Meng wrote:
> >> >> >>> Hi Andrew,
> >> >> >>>
> >> >> >>> On Sun, Aug 9, 2015 at 9:08 AM, Andrew Bradford
> >> >> >>> <andrew@bradfordembedded.com> wrote:
> >> >> >>> > Hi Simon,
> >> >> >>> >
> >> >> >>> > On 08/08 10:18, Simon Glass wrote:
> >> >> >>> >> Hi,
> >> >> >>> >>
> >> >> >>> >> On 7 August 2015 at 06:44, Bin Meng <bmeng.cn@gmail.com> wrote:
> >> >> >>> >> > On Fri, Aug 7, 2015 at 8:36 PM, Andrew Bradford
> >> >> >>> >> > <andrew@bradfordembedded.com> wrote:
> >> >> >>> >> >> From: Andrew Bradford <andrew.bradford@kodakalaris.com>
> >> >> >>> >> >>
> >> >> >>> >> >> Allow for configuration of FSP UPD from the device tree which will
> >> >> >>> >> >> override any settings which the FSP was built with itself.
> >> >> >>> >> >>
> >> >> >>> >> >> Modify the MinnowMax and BayleyBay boards to transfer sensible UPD
> >> >> >>> >> >> settings from the Intel FSPv4 Gold release to the respective dts files,
> >> >> >>> >> >> with the condition that the memory-down parameters for MinnowMax are
> >> >> >>> >> >> also used.
> >> >> >>> >> >>
> >> >> >>> >> >> Signed-off-by: Andrew Bradford <andrew.bradford@kodakalaris.com>
> >> >> >>> >> >> ---
> >> >> >>> >> >>
> >> >> >>> >> >
> >> >> >>> >> > Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> >> >> >>> >> > Tested-by: Bin Meng <bmeng.cn@gmail.com>
> >> >> >>> >> >
> >> >> >>> >>
> >> >> >>> >> Acked-by: Simon Glass <sjg@chromium.org>
> >> >> >>> >> Tested on minnowmax:
> >> >> >>> >> Tested-by: Simon Glass <sjg@chromium.org>
> >> >> >>> >>
> >> >> >>> >> I found that I need to remove two properties from the minnowmax.dts:
> >> >> >>> >>
> >> >> >>> >> - fsp,enable-xhci needs to be removed as this does not work in U-Boot
> >> >> >>> >> at present and stops EHCI from working
> >> >> >>> >> - fsp,mrc-debug-msg needs to be removed to prevent debug information
> >> >> >>> >> being displayed
> >> >> >>> >>
> >> >> >>> >> I plan to apply this with these changes - please let me know if this
> >> >> >>> >> doesn't suit.
> >> >> >>> >
> >> >> >>> > I'm OK with disabling xhci and the MRC debug output in the FSP.
> >> >> >>> >
> >> >> >>> > But if xhci is disabled then I believe when Linux boots that the USB 3.0
> >> >> >>> > port on Minnow Max will only act as a USB 2.0 port.  That u-boot doesn't
> >> >> >>> > yet have working XHCI on E3800 means there is a tradeoff and I wasn't
> >> >> >>> > sure which was a better choice.
> >> >> >>>
> >> >> >>> Does these xHCI ports on MinnowMax work fully on Linux kernel? If it
> >> >> >>> works, I'd rather we keep fsp,enable-xhci in the U-Boot.
> >> >> >>
> >> >> >> I believe that the xhci port does work on Minnow Max in Linux but I do
> >> >> >> not have a board so I'm unable to test, sorry.
> >> >> >>
> >> >> >
> >> >> > OK, my test shows that ehci works fine in U-Boot on Bayley Bay.
> >> >> >
> >> >> > Hi Simon,
> >> >> >
> >> >> > What do you think regarding to xhci vs. ehci in U-Boot?
> >> >>
> >> >> The problem is that USB is then broken in U-Boot. I think it is better
> >> >> to limit the speed for the moment until we have that fixed. It is
> >> >> quite useful to be able to use a keyboard or USB stick in U-Boot.
> >> >>
> >> >> With my testing the bottom (blue) port works fine but the top port
> >> >> does not. This happens regardless of the xhci setting.
> >> >
> >> > Minnowmax has a USB power switch enable which determines if the VBUS2
> >> > net is turned on or not, which will supply or not supply power to the
> >> > USB 2.0 port.  The blue USB 3.0 port also has an enable.  Both enables
> >> > and the USB ports themselves are located on page 16 of the schematic
> >> > that I have.
> >> >
> >> > The switches to enable the VBUS for each port are active high and pulled
> >> > down.  So to turn them on, I believe that's the point of the pinmuxing
> >> > and GPIO settings which are used in the minnowmax.dts.  Can you verify
> >> > if these are correctly turning on VBUS2 (since it sounds like they are
> >> > turning on VBUS1)?  If not, when you turn these GPIO on manually, does
> >> > the USB 2.0 port work correctly?
> >>
> >> I see power on the bottom port but not the top one.
> >
> > OK, that's odd, but likely can be fixed with changes to the pin mux and
> > pad settings in the dts.  I believe that the "pad-offset" for
> > pin_usb_host_en1@0 is wrong and that it should be 0x250 instead of
> > 0x258.
> >
> > diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
> > index d0c0fe6..4988163 100644
> > --- a/arch/x86/dts/minnowmax.dts
> > +++ b/arch/x86/dts/minnowmax.dts
> > @@ -39,7 +39,7 @@
> >
> >                 pin_usb_host_en1@0 {
> >                         gpio-offset = <0x80 9>;
> > -                       pad-offset = <0x258>;
> > +                       pad-offset = <0x250>;
> >                         mode-gpio;
> >                         output-value = <1>;
> >                         direction = <PIN_OUTPUT>;
> >
> > Does that fix it?
> 
> I dug into this a bit and it all seems quite broken:
> 
> - PCI bus configuration does not work in gpio_ich6_pinctrl_init(). I
> will send a patch for this
> - gpio_ich6_get_base() returns a 16-bit word but function is also used
> to read the memory address which holds a 32-bit word
> - Intel's hardware won't let you read the status of an output!

I thought that if you cleared bit 2 in the "pad value" register (iinenb)
for a GPIO that you could read back outputs.  Or am I misunderstanding?

> The last point means that _gpio_ich6_pinctrl_cfg_pin cannot work. We
> need to mirror the lvl register in order to be able to read it.
> 
> I confirmed that with the 'correct' value in the lvl registers both
> USB ports work.

OK, well that's good at least.

Thanks,
Andrew

Hi Andrew,

On 12 August 2015 at 05:52, Andrew Bradford <andrew@bradfordembedded.com> wrote:
> Hi Simon,
>
> On 08/11 21:54, Simon Glass wrote:
>> +Gabriel
>>
>> Hi Andrew,
>>
>> On 11 August 2015 at 09:20, Andrew Bradford <andrew@bradfordembedded.com> wrote:
>> > Hi Simon,
>> >
>> > On 08/11 08:06, Simon Glass wrote:
>> >> Hi Andrew,
>> >>
>> >> On 11 August 2015 at 06:08, Andrew Bradford <andrew@bradfordembedded.com> wrote:
>> >> > Hi Simon,
>> >> >
>> >> > On 08/10 21:07, Simon Glass wrote:
>> >> >> Hi Bin,
>> >> >>
>> >> >> On 10 August 2015 at 20:53, Bin Meng <bmeng.cn@gmail.com> wrote:
>> >> >> > Hi Andrew,
>> >> >> >
>> >> >> > On Mon, Aug 10, 2015 at 7:32 PM, Andrew Bradford
>> >> >> > <andrew@bradfordembedded.com> wrote:
>> >> >> >> Hi Bin,
>> >> >> >>
>> >> >> >> On 08/09 10:52, Bin Meng wrote:
>> >> >> >>> Hi Andrew,
>> >> >> >>>
>> >> >> >>> On Sun, Aug 9, 2015 at 9:08 AM, Andrew Bradford
>> >> >> >>> <andrew@bradfordembedded.com> wrote:
>> >> >> >>> > Hi Simon,
>> >> >> >>> >
>> >> >> >>> > On 08/08 10:18, Simon Glass wrote:
>> >> >> >>> >> Hi,
>> >> >> >>> >>
>> >> >> >>> >> On 7 August 2015 at 06:44, Bin Meng <bmeng.cn@gmail.com> wrote:
>> >> >> >>> >> > On Fri, Aug 7, 2015 at 8:36 PM, Andrew Bradford
>> >> >> >>> >> > <andrew@bradfordembedded.com> wrote:
>> >> >> >>> >> >> From: Andrew Bradford <andrew.bradford@kodakalaris.com>
>> >> >> >>> >> >>
>> >> >> >>> >> >> Allow for configuration of FSP UPD from the device tree which will
>> >> >> >>> >> >> override any settings which the FSP was built with itself.
>> >> >> >>> >> >>
>> >> >> >>> >> >> Modify the MinnowMax and BayleyBay boards to transfer sensible UPD
>> >> >> >>> >> >> settings from the Intel FSPv4 Gold release to the respective dts files,
>> >> >> >>> >> >> with the condition that the memory-down parameters for MinnowMax are
>> >> >> >>> >> >> also used.
>> >> >> >>> >> >>
>> >> >> >>> >> >> Signed-off-by: Andrew Bradford <andrew.bradford@kodakalaris.com>
>> >> >> >>> >> >> ---
>> >> >> >>> >> >>
>> >> >> >>> >> >
>> >> >> >>> >> > Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
>> >> >> >>> >> > Tested-by: Bin Meng <bmeng.cn@gmail.com>
>> >> >> >>> >> >
>> >> >> >>> >>
>> >> >> >>> >> Acked-by: Simon Glass <sjg@chromium.org>
>> >> >> >>> >> Tested on minnowmax:
>> >> >> >>> >> Tested-by: Simon Glass <sjg@chromium.org>
>> >> >> >>> >>
>> >> >> >>> >> I found that I need to remove two properties from the minnowmax.dts:
>> >> >> >>> >>
>> >> >> >>> >> - fsp,enable-xhci needs to be removed as this does not work in U-Boot
>> >> >> >>> >> at present and stops EHCI from working
>> >> >> >>> >> - fsp,mrc-debug-msg needs to be removed to prevent debug information
>> >> >> >>> >> being displayed
>> >> >> >>> >>
>> >> >> >>> >> I plan to apply this with these changes - please let me know if this
>> >> >> >>> >> doesn't suit.
>> >> >> >>> >
>> >> >> >>> > I'm OK with disabling xhci and the MRC debug output in the FSP.
>> >> >> >>> >
>> >> >> >>> > But if xhci is disabled then I believe when Linux boots that the USB 3.0
>> >> >> >>> > port on Minnow Max will only act as a USB 2.0 port.  That u-boot doesn't
>> >> >> >>> > yet have working XHCI on E3800 means there is a tradeoff and I wasn't
>> >> >> >>> > sure which was a better choice.
>> >> >> >>>
>> >> >> >>> Does these xHCI ports on MinnowMax work fully on Linux kernel? If it
>> >> >> >>> works, I'd rather we keep fsp,enable-xhci in the U-Boot.
>> >> >> >>
>> >> >> >> I believe that the xhci port does work on Minnow Max in Linux but I do
>> >> >> >> not have a board so I'm unable to test, sorry.
>> >> >> >>
>> >> >> >
>> >> >> > OK, my test shows that ehci works fine in U-Boot on Bayley Bay.
>> >> >> >
>> >> >> > Hi Simon,
>> >> >> >
>> >> >> > What do you think regarding to xhci vs. ehci in U-Boot?
>> >> >>
>> >> >> The problem is that USB is then broken in U-Boot. I think it is better
>> >> >> to limit the speed for the moment until we have that fixed. It is
>> >> >> quite useful to be able to use a keyboard or USB stick in U-Boot.
>> >> >>
>> >> >> With my testing the bottom (blue) port works fine but the top port
>> >> >> does not. This happens regardless of the xhci setting.
>> >> >
>> >> > Minnowmax has a USB power switch enable which determines if the VBUS2
>> >> > net is turned on or not, which will supply or not supply power to the
>> >> > USB 2.0 port.  The blue USB 3.0 port also has an enable.  Both enables
>> >> > and the USB ports themselves are located on page 16 of the schematic
>> >> > that I have.
>> >> >
>> >> > The switches to enable the VBUS for each port are active high and pulled
>> >> > down.  So to turn them on, I believe that's the point of the pinmuxing
>> >> > and GPIO settings which are used in the minnowmax.dts.  Can you verify
>> >> > if these are correctly turning on VBUS2 (since it sounds like they are
>> >> > turning on VBUS1)?  If not, when you turn these GPIO on manually, does
>> >> > the USB 2.0 port work correctly?
>> >>
>> >> I see power on the bottom port but not the top one.
>> >
>> > OK, that's odd, but likely can be fixed with changes to the pin mux and
>> > pad settings in the dts.  I believe that the "pad-offset" for
>> > pin_usb_host_en1@0 is wrong and that it should be 0x250 instead of
>> > 0x258.
>> >
>> > diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
>> > index d0c0fe6..4988163 100644
>> > --- a/arch/x86/dts/minnowmax.dts
>> > +++ b/arch/x86/dts/minnowmax.dts
>> > @@ -39,7 +39,7 @@
>> >
>> >                 pin_usb_host_en1@0 {
>> >                         gpio-offset = <0x80 9>;
>> > -                       pad-offset = <0x258>;
>> > +                       pad-offset = <0x250>;
>> >                         mode-gpio;
>> >                         output-value = <1>;
>> >                         direction = <PIN_OUTPUT>;
>> >
>> > Does that fix it?
>>
>> I dug into this a bit and it all seems quite broken:
>>
>> - PCI bus configuration does not work in gpio_ich6_pinctrl_init(). I
>> will send a patch for this
>> - gpio_ich6_get_base() returns a 16-bit word but function is also used
>> to read the memory address which holds a 32-bit word
>> - Intel's hardware won't let you read the status of an output!
>
> I thought that if you cleared bit 2 in the "pad value" register (iinenb)
> for a GPIO that you could read back outputs.  Or am I misunderstanding?

That looks right. So Intel's hardware is fine, it just requires
additional configuration. I wonder why we are not setting this?

>
>> The last point means that _gpio_ich6_pinctrl_cfg_pin cannot work. We
>> need to mirror the lvl register in order to be able to read it.
>>
>> I confirmed that with the 'correct' value in the lvl registers both
>> USB ports work.
>
> OK, well that's good at least.
>
> Thanks,
> Andrew

Regards,
Simon

Hi Simon,

On Wed, Aug 12, 2015 at 11:54 AM, Simon Glass <sjg@chromium.org> wrote:
> +Gabriel
>
> Hi Andrew,
>
> On 11 August 2015 at 09:20, Andrew Bradford <andrew@bradfordembedded.com> wrote:
>> Hi Simon,
>>
>> On 08/11 08:06, Simon Glass wrote:
>>> Hi Andrew,
>>>
>>> On 11 August 2015 at 06:08, Andrew Bradford <andrew@bradfordembedded.com> wrote:
>>> > Hi Simon,
>>> >
>>> > On 08/10 21:07, Simon Glass wrote:
>>> >> Hi Bin,
>>> >>
>>> >> On 10 August 2015 at 20:53, Bin Meng <bmeng.cn@gmail.com> wrote:
>>> >> > Hi Andrew,
>>> >> >
>>> >> > On Mon, Aug 10, 2015 at 7:32 PM, Andrew Bradford
>>> >> > <andrew@bradfordembedded.com> wrote:
>>> >> >> Hi Bin,
>>> >> >>
>>> >> >> On 08/09 10:52, Bin Meng wrote:
>>> >> >>> Hi Andrew,
>>> >> >>>
>>> >> >>> On Sun, Aug 9, 2015 at 9:08 AM, Andrew Bradford
>>> >> >>> <andrew@bradfordembedded.com> wrote:
>>> >> >>> > Hi Simon,
>>> >> >>> >
>>> >> >>> > On 08/08 10:18, Simon Glass wrote:
>>> >> >>> >> Hi,
>>> >> >>> >>
>>> >> >>> >> On 7 August 2015 at 06:44, Bin Meng <bmeng.cn@gmail.com> wrote:
>>> >> >>> >> > On Fri, Aug 7, 2015 at 8:36 PM, Andrew Bradford
>>> >> >>> >> > <andrew@bradfordembedded.com> wrote:
>>> >> >>> >> >> From: Andrew Bradford <andrew.bradford@kodakalaris.com>
>>> >> >>> >> >>
>>> >> >>> >> >> Allow for configuration of FSP UPD from the device tree which will
>>> >> >>> >> >> override any settings which the FSP was built with itself.
>>> >> >>> >> >>
>>> >> >>> >> >> Modify the MinnowMax and BayleyBay boards to transfer sensible UPD
>>> >> >>> >> >> settings from the Intel FSPv4 Gold release to the respective dts files,
>>> >> >>> >> >> with the condition that the memory-down parameters for MinnowMax are
>>> >> >>> >> >> also used.
>>> >> >>> >> >>
>>> >> >>> >> >> Signed-off-by: Andrew Bradford <andrew.bradford@kodakalaris.com>
>>> >> >>> >> >> ---
>>> >> >>> >> >>
>>> >> >>> >> >
>>> >> >>> >> > Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
>>> >> >>> >> > Tested-by: Bin Meng <bmeng.cn@gmail.com>
>>> >> >>> >> >
>>> >> >>> >>
>>> >> >>> >> Acked-by: Simon Glass <sjg@chromium.org>
>>> >> >>> >> Tested on minnowmax:
>>> >> >>> >> Tested-by: Simon Glass <sjg@chromium.org>
>>> >> >>> >>
>>> >> >>> >> I found that I need to remove two properties from the minnowmax.dts:
>>> >> >>> >>
>>> >> >>> >> - fsp,enable-xhci needs to be removed as this does not work in U-Boot
>>> >> >>> >> at present and stops EHCI from working
>>> >> >>> >> - fsp,mrc-debug-msg needs to be removed to prevent debug information
>>> >> >>> >> being displayed
>>> >> >>> >>
>>> >> >>> >> I plan to apply this with these changes - please let me know if this
>>> >> >>> >> doesn't suit.
>>> >> >>> >
>>> >> >>> > I'm OK with disabling xhci and the MRC debug output in the FSP.
>>> >> >>> >
>>> >> >>> > But if xhci is disabled then I believe when Linux boots that the USB 3.0
>>> >> >>> > port on Minnow Max will only act as a USB 2.0 port.  That u-boot doesn't
>>> >> >>> > yet have working XHCI on E3800 means there is a tradeoff and I wasn't
>>> >> >>> > sure which was a better choice.
>>> >> >>>
>>> >> >>> Does these xHCI ports on MinnowMax work fully on Linux kernel? If it
>>> >> >>> works, I'd rather we keep fsp,enable-xhci in the U-Boot.
>>> >> >>
>>> >> >> I believe that the xhci port does work on Minnow Max in Linux but I do
>>> >> >> not have a board so I'm unable to test, sorry.
>>> >> >>
>>> >> >
>>> >> > OK, my test shows that ehci works fine in U-Boot on Bayley Bay.
>>> >> >
>>> >> > Hi Simon,
>>> >> >
>>> >> > What do you think regarding to xhci vs. ehci in U-Boot?
>>> >>
>>> >> The problem is that USB is then broken in U-Boot. I think it is better
>>> >> to limit the speed for the moment until we have that fixed. It is
>>> >> quite useful to be able to use a keyboard or USB stick in U-Boot.
>>> >>
>>> >> With my testing the bottom (blue) port works fine but the top port
>>> >> does not. This happens regardless of the xhci setting.
>>> >
>>> > Minnowmax has a USB power switch enable which determines if the VBUS2
>>> > net is turned on or not, which will supply or not supply power to the
>>> > USB 2.0 port.  The blue USB 3.0 port also has an enable.  Both enables
>>> > and the USB ports themselves are located on page 16 of the schematic
>>> > that I have.
>>> >
>>> > The switches to enable the VBUS for each port are active high and pulled
>>> > down.  So to turn them on, I believe that's the point of the pinmuxing
>>> > and GPIO settings which are used in the minnowmax.dts.  Can you verify
>>> > if these are correctly turning on VBUS2 (since it sounds like they are
>>> > turning on VBUS1)?  If not, when you turn these GPIO on manually, does
>>> > the USB 2.0 port work correctly?
>>>
>>> I see power on the bottom port but not the top one.
>>
>> OK, that's odd, but likely can be fixed with changes to the pin mux and
>> pad settings in the dts.  I believe that the "pad-offset" for
>> pin_usb_host_en1@0 is wrong and that it should be 0x250 instead of
>> 0x258.
>>
>> diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
>> index d0c0fe6..4988163 100644
>> --- a/arch/x86/dts/minnowmax.dts
>> +++ b/arch/x86/dts/minnowmax.dts
>> @@ -39,7 +39,7 @@
>>
>>                 pin_usb_host_en1@0 {
>>                         gpio-offset = <0x80 9>;
>> -                       pad-offset = <0x258>;
>> +                       pad-offset = <0x250>;
>>                         mode-gpio;
>>                         output-value = <1>;
>>                         direction = <PIN_OUTPUT>;
>>
>> Does that fix it?
>
> I dug into this a bit and it all seems quite broken:
>
> - PCI bus configuration does not work in gpio_ich6_pinctrl_init(). I
> will send a patch for this

I believe it indeed worked in the past but with the DM PCI conversion
on MinnowMax recently it was broken. That's also why I sent a patch
[1] previously saying that we should explicitly trigger the PCI
enumeration process, as not all DM PCI APIs can trigger the PCI
enumeration, which it is supposed to be as per DM concept.

> - gpio_ich6_get_base() returns a 16-bit word but function is also used
> to read the memory address which holds a 32-bit word
> - Intel's hardware won't let you read the status of an output!
>
> The last point means that _gpio_ich6_pinctrl_cfg_pin cannot work. We
> need to mirror the lvl register in order to be able to read it.
>
> I confirmed that with the 'correct' value in the lvl registers both
> USB ports work.
>

[1]: http://lists.denx.de/pipermail/u-boot/2015-July/220542.html

Regards,
Bin

Hi Simon, Hi Bin,

On 12.08.2015 05:54, Simon Glass wrote:
> +Gabriel
> 
> Hi Andrew,
> 
> On 11 August 2015 at 09:20, Andrew Bradford <andrew@bradfordembedded.com> wrote:
>> Hi Simon,
>>
>> On 08/11 08:06, Simon Glass wrote:
>>> Hi Andrew,
>>>
>>> On 11 August 2015 at 06:08, Andrew Bradford <andrew@bradfordembedded.com> wrote:
>>>> Hi Simon,
>>>>
>>>> On 08/10 21:07, Simon Glass wrote:
>>>>> Hi Bin,
>>>>>
>>>>> On 10 August 2015 at 20:53, Bin Meng <bmeng.cn@gmail.com> wrote:
>>>>>> Hi Andrew,
>>>>>>
>>>>>> On Mon, Aug 10, 2015 at 7:32 PM, Andrew Bradford
>>>>>> <andrew@bradfordembedded.com> wrote:
>>>>>>> Hi Bin,
>>>>>>>
>>>>>>> On 08/09 10:52, Bin Meng wrote:
>>>>>>>> Hi Andrew,
>>>>>>>>
>>>>>>>> On Sun, Aug 9, 2015 at 9:08 AM, Andrew Bradford
>>>>>>>> <andrew@bradfordembedded.com> wrote:
>>>>>>>>> Hi Simon,
>>>>>>>>>
>>>>>>>>> On 08/08 10:18, Simon Glass wrote:
>>>>>>>>>> Hi,
>>>>>>>>>>
>>>>>>>>>> On 7 August 2015 at 06:44, Bin Meng <bmeng.cn@gmail.com> wrote:
>>>>>>>>>>> On Fri, Aug 7, 2015 at 8:36 PM, Andrew Bradford
>>>>>>>>>>> <andrew@bradfordembedded.com> wrote:
>>>>>>>>>>>> From: Andrew Bradford <andrew.bradford@kodakalaris.com>
>>>>>>>>>>>>
>>>>>>>>>>>> Allow for configuration of FSP UPD from the device tree which will
>>>>>>>>>>>> override any settings which the FSP was built with itself.
>>>>>>>>>>>>
>>>>>>>>>>>> Modify the MinnowMax and BayleyBay boards to transfer sensible UPD
>>>>>>>>>>>> settings from the Intel FSPv4 Gold release to the respective dts files,
>>>>>>>>>>>> with the condition that the memory-down parameters for MinnowMax are
>>>>>>>>>>>> also used.
>>>>>>>>>>>>
>>>>>>>>>>>> Signed-off-by: Andrew Bradford <andrew.bradford@kodakalaris.com>
>>>>>>>>>>>> ---
>>>>>>>>>>>>
>>>>>>>>>>>
>>>>>>>>>>> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
>>>>>>>>>>> Tested-by: Bin Meng <bmeng.cn@gmail.com>
>>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>> Acked-by: Simon Glass <sjg@chromium.org>
>>>>>>>>>> Tested on minnowmax:
>>>>>>>>>> Tested-by: Simon Glass <sjg@chromium.org>
>>>>>>>>>>
>>>>>>>>>> I found that I need to remove two properties from the minnowmax.dts:
>>>>>>>>>>
>>>>>>>>>> - fsp,enable-xhci needs to be removed as this does not work in U-Boot
>>>>>>>>>> at present and stops EHCI from working
>>>>>>>>>> - fsp,mrc-debug-msg needs to be removed to prevent debug information
>>>>>>>>>> being displayed
>>>>>>>>>>
>>>>>>>>>> I plan to apply this with these changes - please let me know if this
>>>>>>>>>> doesn't suit.
>>>>>>>>>
>>>>>>>>> I'm OK with disabling xhci and the MRC debug output in the FSP.
>>>>>>>>>
>>>>>>>>> But if xhci is disabled then I believe when Linux boots that the USB 3.0
>>>>>>>>> port on Minnow Max will only act as a USB 2.0 port.  That u-boot doesn't
>>>>>>>>> yet have working XHCI on E3800 means there is a tradeoff and I wasn't
>>>>>>>>> sure which was a better choice.
>>>>>>>>
>>>>>>>> Does these xHCI ports on MinnowMax work fully on Linux kernel? If it
>>>>>>>> works, I'd rather we keep fsp,enable-xhci in the U-Boot.
>>>>>>>
>>>>>>> I believe that the xhci port does work on Minnow Max in Linux but I do
>>>>>>> not have a board so I'm unable to test, sorry.
>>>>>>>
>>>>>>
>>>>>> OK, my test shows that ehci works fine in U-Boot on Bayley Bay.
>>>>>>
>>>>>> Hi Simon,
>>>>>>
>>>>>> What do you think regarding to xhci vs. ehci in U-Boot?
>>>>>
>>>>> The problem is that USB is then broken in U-Boot. I think it is better
>>>>> to limit the speed for the moment until we have that fixed. It is
>>>>> quite useful to be able to use a keyboard or USB stick in U-Boot.
>>>>>
>>>>> With my testing the bottom (blue) port works fine but the top port
>>>>> does not. This happens regardless of the xhci setting.
>>>>
>>>> Minnowmax has a USB power switch enable which determines if the VBUS2
>>>> net is turned on or not, which will supply or not supply power to the
>>>> USB 2.0 port.  The blue USB 3.0 port also has an enable.  Both enables
>>>> and the USB ports themselves are located on page 16 of the schematic
>>>> that I have.
>>>>
>>>> The switches to enable the VBUS for each port are active high and pulled
>>>> down.  So to turn them on, I believe that's the point of the pinmuxing
>>>> and GPIO settings which are used in the minnowmax.dts.  Can you verify
>>>> if these are correctly turning on VBUS2 (since it sounds like they are
>>>> turning on VBUS1)?  If not, when you turn these GPIO on manually, does
>>>> the USB 2.0 port work correctly?
>>>
>>> I see power on the bottom port but not the top one.
>>
>> OK, that's odd, but likely can be fixed with changes to the pin mux and
>> pad settings in the dts.  I believe that the "pad-offset" for
>> pin_usb_host_en1@0 is wrong and that it should be 0x250 instead of
>> 0x258.
>>
>> diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
>> index d0c0fe6..4988163 100644
>> --- a/arch/x86/dts/minnowmax.dts
>> +++ b/arch/x86/dts/minnowmax.dts
>> @@ -39,7 +39,7 @@
>>
>>                  pin_usb_host_en1@0 {
>>                          gpio-offset = <0x80 9>;
>> -                       pad-offset = <0x258>;
>> +                       pad-offset = <0x250>;
>>                          mode-gpio;
>>                          output-value = <1>;
>>                          direction = <PIN_OUTPUT>;
>>
>> Does that fix it?
> 
> I dug into this a bit and it all seems quite broken:
> 
> - PCI bus configuration does not work in gpio_ich6_pinctrl_init(). I
> will send a patch for this
> - gpio_ich6_get_base() returns a 16-bit word but function is also used
> to read the memory address which holds a 32-bit word
> - Intel's hardware won't let you read the status of an output!
> 
> The last point means that _gpio_ich6_pinctrl_cfg_pin cannot work. We
> need to mirror the lvl register in order to be able to read it.
> 
> I confirmed that with the 'correct' value in the lvl registers both
> USB ports work.

I'm currently struggling with the USB EHCI ports on my custom Bay
Trail x86 board. With the current U-Boot, cloned from the MinnowMAX,
only some of the USB EHCI ports are enabled / available. Here
the "usb tree" output with 3 USB keys installed:

=> usb tree
USB device tree:
  1  Hub (480 Mb/s, 0mA)
  |  u-boot EHCI Host Controller 
  |
  +-2  Hub (480 Mb/s, 0mA)
    |
    +-3  Hub (480 Mb/s, 100mA)
    | |
    | +-4  Hub (12 Mb/s, 100mA)
    |    
    +-5  Mass Storage (480 Mb/s, 200mA)
         JetFlash Mass Storage Device 3281440601

When I first start the original (AMI) BIOS on this custom board,
and then reboot into U-Boot (without a power-cycle), I see this
configuration:

=> usb tree
USB device tree:
  1  Hub (480 Mb/s, 0mA)
  |  u-boot EHCI Host Controller 
  |
  +-2  Hub (480 Mb/s, 0mA)
    |
    +-3  Hub (480 Mb/s, 100mA)
    | |
    | +-4  Hub (12 Mb/s, 100mA)
    |    
    +-5  Hub (480 Mb/s, 0mA)
    | |
    | +-6  Mass Storage (480 Mb/s, 200mA)
    | |    Kingston DataTraveler 2.0 50E549C688C4BE7189942766
    | |  
    | +-7  Mass Storage (480 Mb/s, 98mA)
    |      USBest Technology USB Mass Storage Device 09092207fbf0c4
    |    
    +-8  Mass Storage (480 Mb/s, 200mA)
         JetFlash Mass Storage Device 3281440601

So now all 3 USB sticks are detected.

It doesn't seem to be a problem with missing USB power switch
enabling via some GPIOs. I've checked the schematics and all ports
should have power enabled.

Do you have any quick ideas, what might be missing to enable all
4 EHCI ports on Bay Trail? There seems to be a per-port disable
feature which might be involved. I'm still pretty new to x86, and
I'm struggling with finding the correct datasheet for this. So any
hints are really appreciated.

Thanks,
Stefan

Hi Stefan,

On 8 March 2016 at 09:45, Stefan Roese <sr@denx.de> wrote:
> Hi Simon, Hi Bin,
>
> On 12.08.2015 05:54, Simon Glass wrote:
>> +Gabriel
>>
>> Hi Andrew,
>>
>> On 11 August 2015 at 09:20, Andrew Bradford <andrew@bradfordembedded.com> wrote:
>>> Hi Simon,
>>>
>>> On 08/11 08:06, Simon Glass wrote:
>>>> Hi Andrew,
>>>>
>>>> On 11 August 2015 at 06:08, Andrew Bradford <andrew@bradfordembedded.com> wrote:
>>>>> Hi Simon,
>>>>>
>>>>> On 08/10 21:07, Simon Glass wrote:
>>>>>> Hi Bin,
>>>>>>
>>>>>> On 10 August 2015 at 20:53, Bin Meng <bmeng.cn@gmail.com> wrote:
>>>>>>> Hi Andrew,
>>>>>>>
>>>>>>> On Mon, Aug 10, 2015 at 7:32 PM, Andrew Bradford
>>>>>>> <andrew@bradfordembedded.com> wrote:
>>>>>>>> Hi Bin,
>>>>>>>>
>>>>>>>> On 08/09 10:52, Bin Meng wrote:
>>>>>>>>> Hi Andrew,
>>>>>>>>>
>>>>>>>>> On Sun, Aug 9, 2015 at 9:08 AM, Andrew Bradford
>>>>>>>>> <andrew@bradfordembedded.com> wrote:
>>>>>>>>>> Hi Simon,
>>>>>>>>>>
>>>>>>>>>> On 08/08 10:18, Simon Glass wrote:
>>>>>>>>>>> Hi,
>>>>>>>>>>>
>>>>>>>>>>> On 7 August 2015 at 06:44, Bin Meng <bmeng.cn@gmail.com> wrote:
>>>>>>>>>>>> On Fri, Aug 7, 2015 at 8:36 PM, Andrew Bradford
>>>>>>>>>>>> <andrew@bradfordembedded.com> wrote:
>>>>>>>>>>>>> From: Andrew Bradford <andrew.bradford@kodakalaris.com>
>>>>>>>>>>>>>
>>>>>>>>>>>>> Allow for configuration of FSP UPD from the device tree which will
>>>>>>>>>>>>> override any settings which the FSP was built with itself.
>>>>>>>>>>>>>
>>>>>>>>>>>>> Modify the MinnowMax and BayleyBay boards to transfer sensible UPD
>>>>>>>>>>>>> settings from the Intel FSPv4 Gold release to the respective dts files,
>>>>>>>>>>>>> with the condition that the memory-down parameters for MinnowMax are
>>>>>>>>>>>>> also used.
>>>>>>>>>>>>>
>>>>>>>>>>>>> Signed-off-by: Andrew Bradford <andrew.bradford@kodakalaris.com>
>>>>>>>>>>>>> ---
>>>>>>>>>>>>>
>>>>>>>>>>>>
>>>>>>>>>>>> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
>>>>>>>>>>>> Tested-by: Bin Meng <bmeng.cn@gmail.com>
>>>>>>>>>>>>
>>>>>>>>>>>
>>>>>>>>>>> Acked-by: Simon Glass <sjg@chromium.org>
>>>>>>>>>>> Tested on minnowmax:
>>>>>>>>>>> Tested-by: Simon Glass <sjg@chromium.org>
>>>>>>>>>>>
>>>>>>>>>>> I found that I need to remove two properties from the minnowmax.dts:
>>>>>>>>>>>
>>>>>>>>>>> - fsp,enable-xhci needs to be removed as this does not work in U-Boot
>>>>>>>>>>> at present and stops EHCI from working
>>>>>>>>>>> - fsp,mrc-debug-msg needs to be removed to prevent debug information
>>>>>>>>>>> being displayed
>>>>>>>>>>>
>>>>>>>>>>> I plan to apply this with these changes - please let me know if this
>>>>>>>>>>> doesn't suit.
>>>>>>>>>>
>>>>>>>>>> I'm OK with disabling xhci and the MRC debug output in the FSP.
>>>>>>>>>>
>>>>>>>>>> But if xhci is disabled then I believe when Linux boots that the USB 3.0
>>>>>>>>>> port on Minnow Max will only act as a USB 2.0 port.  That u-boot doesn't
>>>>>>>>>> yet have working XHCI on E3800 means there is a tradeoff and I wasn't
>>>>>>>>>> sure which was a better choice.
>>>>>>>>>
>>>>>>>>> Does these xHCI ports on MinnowMax work fully on Linux kernel? If it
>>>>>>>>> works, I'd rather we keep fsp,enable-xhci in the U-Boot.
>>>>>>>>
>>>>>>>> I believe that the xhci port does work on Minnow Max in Linux but I do
>>>>>>>> not have a board so I'm unable to test, sorry.
>>>>>>>>
>>>>>>>
>>>>>>> OK, my test shows that ehci works fine in U-Boot on Bayley Bay.
>>>>>>>
>>>>>>> Hi Simon,
>>>>>>>
>>>>>>> What do you think regarding to xhci vs. ehci in U-Boot?
>>>>>>
>>>>>> The problem is that USB is then broken in U-Boot. I think it is better
>>>>>> to limit the speed for the moment until we have that fixed. It is
>>>>>> quite useful to be able to use a keyboard or USB stick in U-Boot.
>>>>>>
>>>>>> With my testing the bottom (blue) port works fine but the top port
>>>>>> does not. This happens regardless of the xhci setting.
>>>>>
>>>>> Minnowmax has a USB power switch enable which determines if the VBUS2
>>>>> net is turned on or not, which will supply or not supply power to the
>>>>> USB 2.0 port.  The blue USB 3.0 port also has an enable.  Both enables
>>>>> and the USB ports themselves are located on page 16 of the schematic
>>>>> that I have.
>>>>>
>>>>> The switches to enable the VBUS for each port are active high and pulled
>>>>> down.  So to turn them on, I believe that's the point of the pinmuxing
>>>>> and GPIO settings which are used in the minnowmax.dts.  Can you verify
>>>>> if these are correctly turning on VBUS2 (since it sounds like they are
>>>>> turning on VBUS1)?  If not, when you turn these GPIO on manually, does
>>>>> the USB 2.0 port work correctly?
>>>>
>>>> I see power on the bottom port but not the top one.
>>>
>>> OK, that's odd, but likely can be fixed with changes to the pin mux and
>>> pad settings in the dts.  I believe that the "pad-offset" for
>>> pin_usb_host_en1@0 is wrong and that it should be 0x250 instead of
>>> 0x258.
>>>
>>> diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
>>> index d0c0fe6..4988163 100644
>>> --- a/arch/x86/dts/minnowmax.dts
>>> +++ b/arch/x86/dts/minnowmax.dts
>>> @@ -39,7 +39,7 @@
>>>
>>>                  pin_usb_host_en1@0 {
>>>                          gpio-offset = <0x80 9>;
>>> -                       pad-offset = <0x258>;
>>> +                       pad-offset = <0x250>;
>>>                          mode-gpio;
>>>                          output-value = <1>;
>>>                          direction = <PIN_OUTPUT>;
>>>
>>> Does that fix it?
>>
>> I dug into this a bit and it all seems quite broken:
>>
>> - PCI bus configuration does not work in gpio_ich6_pinctrl_init(). I
>> will send a patch for this
>> - gpio_ich6_get_base() returns a 16-bit word but function is also used
>> to read the memory address which holds a 32-bit word
>> - Intel's hardware won't let you read the status of an output!
>>
>> The last point means that _gpio_ich6_pinctrl_cfg_pin cannot work. We
>> need to mirror the lvl register in order to be able to read it.
>>
>> I confirmed that with the 'correct' value in the lvl registers both
>> USB ports work.
>
> I'm currently struggling with the USB EHCI ports on my custom Bay
> Trail x86 board. With the current U-Boot, cloned from the MinnowMAX,
> only some of the USB EHCI ports are enabled / available. Here
> the "usb tree" output with 3 USB keys installed:
>
> => usb tree
> USB device tree:
>   1  Hub (480 Mb/s, 0mA)
>   |  u-boot EHCI Host Controller
>   |
>   +-2  Hub (480 Mb/s, 0mA)
>     |
>     +-3  Hub (480 Mb/s, 100mA)
>     | |
>     | +-4  Hub (12 Mb/s, 100mA)
>     |
>     +-5  Mass Storage (480 Mb/s, 200mA)
>          JetFlash Mass Storage Device 3281440601
>
> When I first start the original (AMI) BIOS on this custom board,
> and then reboot into U-Boot (without a power-cycle), I see this
> configuration:
>
> => usb tree
> USB device tree:
>   1  Hub (480 Mb/s, 0mA)
>   |  u-boot EHCI Host Controller
>   |
>   +-2  Hub (480 Mb/s, 0mA)
>     |
>     +-3  Hub (480 Mb/s, 100mA)
>     | |
>     | +-4  Hub (12 Mb/s, 100mA)
>     |
>     +-5  Hub (480 Mb/s, 0mA)
>     | |
>     | +-6  Mass Storage (480 Mb/s, 200mA)
>     | |    Kingston DataTraveler 2.0 50E549C688C4BE7189942766
>     | |
>     | +-7  Mass Storage (480 Mb/s, 98mA)
>     |      USBest Technology USB Mass Storage Device 09092207fbf0c4
>     |
>     +-8  Mass Storage (480 Mb/s, 200mA)
>          JetFlash Mass Storage Device 3281440601
>
> So now all 3 USB sticks are detected.
>
> It doesn't seem to be a problem with missing USB power switch
> enabling via some GPIOs. I've checked the schematics and all ports
> should have power enabled.
>
> Do you have any quick ideas, what might be missing to enable all
> 4 EHCI ports on Bay Trail? There seems to be a per-port disable
> feature which might be involved. I'm still pretty new to x86, and
> I'm struggling with finding the correct datasheet for this. So any
> hints are really appreciated.

It might be worth checking the pci bus device list in both cases.
Perhaps one of the USB ports is disabled?

Regards,
Simon

Hi Simon,

On 08.03.2016 17:54, Simon Glass wrote:
> Hi Stefan,
> 
> On 8 March 2016 at 09:45, Stefan Roese <sr@denx.de> wrote:
>> Hi Simon, Hi Bin,
>>
>> On 12.08.2015 05:54, Simon Glass wrote:
>>> +Gabriel
>>>
>>> Hi Andrew,
>>>
>>> On 11 August 2015 at 09:20, Andrew Bradford <andrew@bradfordembedded.com> wrote:
>>>> Hi Simon,
>>>>
>>>> On 08/11 08:06, Simon Glass wrote:
>>>>> Hi Andrew,
>>>>>
>>>>> On 11 August 2015 at 06:08, Andrew Bradford <andrew@bradfordembedded.com> wrote:
>>>>>> Hi Simon,
>>>>>>
>>>>>> On 08/10 21:07, Simon Glass wrote:
>>>>>>> Hi Bin,
>>>>>>>
>>>>>>> On 10 August 2015 at 20:53, Bin Meng <bmeng.cn@gmail.com> wrote:
>>>>>>>> Hi Andrew,
>>>>>>>>
>>>>>>>> On Mon, Aug 10, 2015 at 7:32 PM, Andrew Bradford
>>>>>>>> <andrew@bradfordembedded.com> wrote:
>>>>>>>>> Hi Bin,
>>>>>>>>>
>>>>>>>>> On 08/09 10:52, Bin Meng wrote:
>>>>>>>>>> Hi Andrew,
>>>>>>>>>>
>>>>>>>>>> On Sun, Aug 9, 2015 at 9:08 AM, Andrew Bradford
>>>>>>>>>> <andrew@bradfordembedded.com> wrote:
>>>>>>>>>>> Hi Simon,
>>>>>>>>>>>
>>>>>>>>>>> On 08/08 10:18, Simon Glass wrote:
>>>>>>>>>>>> Hi,
>>>>>>>>>>>>
>>>>>>>>>>>> On 7 August 2015 at 06:44, Bin Meng <bmeng.cn@gmail.com> wrote:
>>>>>>>>>>>>> On Fri, Aug 7, 2015 at 8:36 PM, Andrew Bradford
>>>>>>>>>>>>> <andrew@bradfordembedded.com> wrote:
>>>>>>>>>>>>>> From: Andrew Bradford <andrew.bradford@kodakalaris.com>
>>>>>>>>>>>>>>
>>>>>>>>>>>>>> Allow for configuration of FSP UPD from the device tree which will
>>>>>>>>>>>>>> override any settings which the FSP was built with itself.
>>>>>>>>>>>>>>
>>>>>>>>>>>>>> Modify the MinnowMax and BayleyBay boards to transfer sensible UPD
>>>>>>>>>>>>>> settings from the Intel FSPv4 Gold release to the respective dts files,
>>>>>>>>>>>>>> with the condition that the memory-down parameters for MinnowMax are
>>>>>>>>>>>>>> also used.
>>>>>>>>>>>>>>
>>>>>>>>>>>>>> Signed-off-by: Andrew Bradford <andrew.bradford@kodakalaris.com>
>>>>>>>>>>>>>> ---
>>>>>>>>>>>>>>
>>>>>>>>>>>>>
>>>>>>>>>>>>> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
>>>>>>>>>>>>> Tested-by: Bin Meng <bmeng.cn@gmail.com>
>>>>>>>>>>>>>
>>>>>>>>>>>>
>>>>>>>>>>>> Acked-by: Simon Glass <sjg@chromium.org>
>>>>>>>>>>>> Tested on minnowmax:
>>>>>>>>>>>> Tested-by: Simon Glass <sjg@chromium.org>
>>>>>>>>>>>>
>>>>>>>>>>>> I found that I need to remove two properties from the minnowmax.dts:
>>>>>>>>>>>>
>>>>>>>>>>>> - fsp,enable-xhci needs to be removed as this does not work in U-Boot
>>>>>>>>>>>> at present and stops EHCI from working
>>>>>>>>>>>> - fsp,mrc-debug-msg needs to be removed to prevent debug information
>>>>>>>>>>>> being displayed
>>>>>>>>>>>>
>>>>>>>>>>>> I plan to apply this with these changes - please let me know if this
>>>>>>>>>>>> doesn't suit.
>>>>>>>>>>>
>>>>>>>>>>> I'm OK with disabling xhci and the MRC debug output in the FSP.
>>>>>>>>>>>
>>>>>>>>>>> But if xhci is disabled then I believe when Linux boots that the USB 3.0
>>>>>>>>>>> port on Minnow Max will only act as a USB 2.0 port.  That u-boot doesn't
>>>>>>>>>>> yet have working XHCI on E3800 means there is a tradeoff and I wasn't
>>>>>>>>>>> sure which was a better choice.
>>>>>>>>>>
>>>>>>>>>> Does these xHCI ports on MinnowMax work fully on Linux kernel? If it
>>>>>>>>>> works, I'd rather we keep fsp,enable-xhci in the U-Boot.
>>>>>>>>>
>>>>>>>>> I believe that the xhci port does work on Minnow Max in Linux but I do
>>>>>>>>> not have a board so I'm unable to test, sorry.
>>>>>>>>>
>>>>>>>>
>>>>>>>> OK, my test shows that ehci works fine in U-Boot on Bayley Bay.
>>>>>>>>
>>>>>>>> Hi Simon,
>>>>>>>>
>>>>>>>> What do you think regarding to xhci vs. ehci in U-Boot?
>>>>>>>
>>>>>>> The problem is that USB is then broken in U-Boot. I think it is better
>>>>>>> to limit the speed for the moment until we have that fixed. It is
>>>>>>> quite useful to be able to use a keyboard or USB stick in U-Boot.
>>>>>>>
>>>>>>> With my testing the bottom (blue) port works fine but the top port
>>>>>>> does not. This happens regardless of the xhci setting.
>>>>>>
>>>>>> Minnowmax has a USB power switch enable which determines if the VBUS2
>>>>>> net is turned on or not, which will supply or not supply power to the
>>>>>> USB 2.0 port.  The blue USB 3.0 port also has an enable.  Both enables
>>>>>> and the USB ports themselves are located on page 16 of the schematic
>>>>>> that I have.
>>>>>>
>>>>>> The switches to enable the VBUS for each port are active high and pulled
>>>>>> down.  So to turn them on, I believe that's the point of the pinmuxing
>>>>>> and GPIO settings which are used in the minnowmax.dts.  Can you verify
>>>>>> if these are correctly turning on VBUS2 (since it sounds like they are
>>>>>> turning on VBUS1)?  If not, when you turn these GPIO on manually, does
>>>>>> the USB 2.0 port work correctly?
>>>>>
>>>>> I see power on the bottom port but not the top one.
>>>>
>>>> OK, that's odd, but likely can be fixed with changes to the pin mux and
>>>> pad settings in the dts.  I believe that the "pad-offset" for
>>>> pin_usb_host_en1@0 is wrong and that it should be 0x250 instead of
>>>> 0x258.
>>>>
>>>> diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
>>>> index d0c0fe6..4988163 100644
>>>> --- a/arch/x86/dts/minnowmax.dts
>>>> +++ b/arch/x86/dts/minnowmax.dts
>>>> @@ -39,7 +39,7 @@
>>>>
>>>>                   pin_usb_host_en1@0 {
>>>>                           gpio-offset = <0x80 9>;
>>>> -                       pad-offset = <0x258>;
>>>> +                       pad-offset = <0x250>;
>>>>                           mode-gpio;
>>>>                           output-value = <1>;
>>>>                           direction = <PIN_OUTPUT>;
>>>>
>>>> Does that fix it?
>>>
>>> I dug into this a bit and it all seems quite broken:
>>>
>>> - PCI bus configuration does not work in gpio_ich6_pinctrl_init(). I
>>> will send a patch for this
>>> - gpio_ich6_get_base() returns a 16-bit word but function is also used
>>> to read the memory address which holds a 32-bit word
>>> - Intel's hardware won't let you read the status of an output!
>>>
>>> The last point means that _gpio_ich6_pinctrl_cfg_pin cannot work. We
>>> need to mirror the lvl register in order to be able to read it.
>>>
>>> I confirmed that with the 'correct' value in the lvl registers both
>>> USB ports work.
>>
>> I'm currently struggling with the USB EHCI ports on my custom Bay
>> Trail x86 board. With the current U-Boot, cloned from the MinnowMAX,
>> only some of the USB EHCI ports are enabled / available. Here
>> the "usb tree" output with 3 USB keys installed:
>>
>> => usb tree
>> USB device tree:
>>    1  Hub (480 Mb/s, 0mA)
>>    |  u-boot EHCI Host Controller
>>    |
>>    +-2  Hub (480 Mb/s, 0mA)
>>      |
>>      +-3  Hub (480 Mb/s, 100mA)
>>      | |
>>      | +-4  Hub (12 Mb/s, 100mA)
>>      |
>>      +-5  Mass Storage (480 Mb/s, 200mA)
>>           JetFlash Mass Storage Device 3281440601
>>
>> When I first start the original (AMI) BIOS on this custom board,
>> and then reboot into U-Boot (without a power-cycle), I see this
>> configuration:
>>
>> => usb tree
>> USB device tree:
>>    1  Hub (480 Mb/s, 0mA)
>>    |  u-boot EHCI Host Controller
>>    |
>>    +-2  Hub (480 Mb/s, 0mA)
>>      |
>>      +-3  Hub (480 Mb/s, 100mA)
>>      | |
>>      | +-4  Hub (12 Mb/s, 100mA)
>>      |
>>      +-5  Hub (480 Mb/s, 0mA)
>>      | |
>>      | +-6  Mass Storage (480 Mb/s, 200mA)
>>      | |    Kingston DataTraveler 2.0 50E549C688C4BE7189942766
>>      | |
>>      | +-7  Mass Storage (480 Mb/s, 98mA)
>>      |      USBest Technology USB Mass Storage Device 09092207fbf0c4
>>      |
>>      +-8  Mass Storage (480 Mb/s, 200mA)
>>           JetFlash Mass Storage Device 3281440601
>>
>> So now all 3 USB sticks are detected.
>>
>> It doesn't seem to be a problem with missing USB power switch
>> enabling via some GPIOs. I've checked the schematics and all ports
>> should have power enabled.
>>
>> Do you have any quick ideas, what might be missing to enable all
>> 4 EHCI ports on Bay Trail? There seems to be a per-port disable
>> feature which might be involved. I'm still pretty new to x86, and
>> I'm struggling with finding the correct datasheet for this. So any
>> hints are really appreciated.
> 
> It might be worth checking the pci bus device list in both cases.
> Perhaps one of the USB ports is disabled?

IIUTC, its only one PCI device, that handles all EHCI USB 2.0 ports.
In both cases its this output:

=> pci
Scanning PCI devices on bus 0                                                                                                                                                       
BusDevFun  VendorId   DeviceId   Device Class       Sub-Class

Hi Stefan,

On 8 March 2016 at 10:41, Stefan Roese <sr@denx.de> wrote:
> Hi Simon,
>
> On 08.03.2016 17:54, Simon Glass wrote:
>> Hi Stefan,
>>
>> On 8 March 2016 at 09:45, Stefan Roese <sr@denx.de> wrote:
>>> Hi Simon, Hi Bin,
>>>
>>> On 12.08.2015 05:54, Simon Glass wrote:
>>>> +Gabriel
>>>>
>>>> Hi Andrew,
>>>>
>>>> On 11 August 2015 at 09:20, Andrew Bradford <andrew@bradfordembedded.com> wrote:
>>>>> Hi Simon,
>>>>>
>>>>> On 08/11 08:06, Simon Glass wrote:
>>>>>> Hi Andrew,
>>>>>>
>>>>>> On 11 August 2015 at 06:08, Andrew Bradford <andrew@bradfordembedded.com> wrote:
>>>>>>> Hi Simon,
>>>>>>>
>>>>>>> On 08/10 21:07, Simon Glass wrote:
>>>>>>>> Hi Bin,
>>>>>>>>
>>>>>>>> On 10 August 2015 at 20:53, Bin Meng <bmeng.cn@gmail.com> wrote:
>>>>>>>>> Hi Andrew,
>>>>>>>>>
>>>>>>>>> On Mon, Aug 10, 2015 at 7:32 PM, Andrew Bradford
>>>>>>>>> <andrew@bradfordembedded.com> wrote:
>>>>>>>>>> Hi Bin,
>>>>>>>>>>
>>>>>>>>>> On 08/09 10:52, Bin Meng wrote:
>>>>>>>>>>> Hi Andrew,
>>>>>>>>>>>
>>>>>>>>>>> On Sun, Aug 9, 2015 at 9:08 AM, Andrew Bradford
>>>>>>>>>>> <andrew@bradfordembedded.com> wrote:
>>>>>>>>>>>> Hi Simon,
>>>>>>>>>>>>
>>>>>>>>>>>> On 08/08 10:18, Simon Glass wrote:
>>>>>>>>>>>>> Hi,
>>>>>>>>>>>>>
>>>>>>>>>>>>> On 7 August 2015 at 06:44, Bin Meng <bmeng.cn@gmail.com> wrote:
>>>>>>>>>>>>>> On Fri, Aug 7, 2015 at 8:36 PM, Andrew Bradford
>>>>>>>>>>>>>> <andrew@bradfordembedded.com> wrote:
>>>>>>>>>>>>>>> From: Andrew Bradford <andrew.bradford@kodakalaris.com>
>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>> Allow for configuration of FSP UPD from the device tree which will
>>>>>>>>>>>>>>> override any settings which the FSP was built with itself.
>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>> Modify the MinnowMax and BayleyBay boards to transfer sensible UPD
>>>>>>>>>>>>>>> settings from the Intel FSPv4 Gold release to the respective dts files,
>>>>>>>>>>>>>>> with the condition that the memory-down parameters for MinnowMax are
>>>>>>>>>>>>>>> also used.
>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>> Signed-off-by: Andrew Bradford <andrew.bradford@kodakalaris.com>
>>>>>>>>>>>>>>> ---
>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>
>>>>>>>>>>>>>> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
>>>>>>>>>>>>>> Tested-by: Bin Meng <bmeng.cn@gmail.com>
>>>>>>>>>>>>>>
>>>>>>>>>>>>>
>>>>>>>>>>>>> Acked-by: Simon Glass <sjg@chromium.org>
>>>>>>>>>>>>> Tested on minnowmax:
>>>>>>>>>>>>> Tested-by: Simon Glass <sjg@chromium.org>
>>>>>>>>>>>>>
>>>>>>>>>>>>> I found that I need to remove two properties from the minnowmax.dts:
>>>>>>>>>>>>>
>>>>>>>>>>>>> - fsp,enable-xhci needs to be removed as this does not work in U-Boot
>>>>>>>>>>>>> at present and stops EHCI from working
>>>>>>>>>>>>> - fsp,mrc-debug-msg needs to be removed to prevent debug information
>>>>>>>>>>>>> being displayed
>>>>>>>>>>>>>
>>>>>>>>>>>>> I plan to apply this with these changes - please let me know if this
>>>>>>>>>>>>> doesn't suit.
>>>>>>>>>>>>
>>>>>>>>>>>> I'm OK with disabling xhci and the MRC debug output in the FSP.
>>>>>>>>>>>>
>>>>>>>>>>>> But if xhci is disabled then I believe when Linux boots that the USB 3.0
>>>>>>>>>>>> port on Minnow Max will only act as a USB 2.0 port.  That u-boot doesn't
>>>>>>>>>>>> yet have working XHCI on E3800 means there is a tradeoff and I wasn't
>>>>>>>>>>>> sure which was a better choice.
>>>>>>>>>>>
>>>>>>>>>>> Does these xHCI ports on MinnowMax work fully on Linux kernel? If it
>>>>>>>>>>> works, I'd rather we keep fsp,enable-xhci in the U-Boot.
>>>>>>>>>>
>>>>>>>>>> I believe that the xhci port does work on Minnow Max in Linux but I do
>>>>>>>>>> not have a board so I'm unable to test, sorry.
>>>>>>>>>>
>>>>>>>>>
>>>>>>>>> OK, my test shows that ehci works fine in U-Boot on Bayley Bay.
>>>>>>>>>
>>>>>>>>> Hi Simon,
>>>>>>>>>
>>>>>>>>> What do you think regarding to xhci vs. ehci in U-Boot?
>>>>>>>>
>>>>>>>> The problem is that USB is then broken in U-Boot. I think it is better
>>>>>>>> to limit the speed for the moment until we have that fixed. It is
>>>>>>>> quite useful to be able to use a keyboard or USB stick in U-Boot.
>>>>>>>>
>>>>>>>> With my testing the bottom (blue) port works fine but the top port
>>>>>>>> does not. This happens regardless of the xhci setting.
>>>>>>>
>>>>>>> Minnowmax has a USB power switch enable which determines if the VBUS2
>>>>>>> net is turned on or not, which will supply or not supply power to the
>>>>>>> USB 2.0 port.  The blue USB 3.0 port also has an enable.  Both enables
>>>>>>> and the USB ports themselves are located on page 16 of the schematic
>>>>>>> that I have.
>>>>>>>
>>>>>>> The switches to enable the VBUS for each port are active high and pulled
>>>>>>> down.  So to turn them on, I believe that's the point of the pinmuxing
>>>>>>> and GPIO settings which are used in the minnowmax.dts.  Can you verify
>>>>>>> if these are correctly turning on VBUS2 (since it sounds like they are
>>>>>>> turning on VBUS1)?  If not, when you turn these GPIO on manually, does
>>>>>>> the USB 2.0 port work correctly?
>>>>>>
>>>>>> I see power on the bottom port but not the top one.
>>>>>
>>>>> OK, that's odd, but likely can be fixed with changes to the pin mux and
>>>>> pad settings in the dts.  I believe that the "pad-offset" for
>>>>> pin_usb_host_en1@0 is wrong and that it should be 0x250 instead of
>>>>> 0x258.
>>>>>
>>>>> diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
>>>>> index d0c0fe6..4988163 100644
>>>>> --- a/arch/x86/dts/minnowmax.dts
>>>>> +++ b/arch/x86/dts/minnowmax.dts
>>>>> @@ -39,7 +39,7 @@
>>>>>
>>>>>                   pin_usb_host_en1@0 {
>>>>>                           gpio-offset = <0x80 9>;
>>>>> -                       pad-offset = <0x258>;
>>>>> +                       pad-offset = <0x250>;
>>>>>                           mode-gpio;
>>>>>                           output-value = <1>;
>>>>>                           direction = <PIN_OUTPUT>;
>>>>>
>>>>> Does that fix it?
>>>>
>>>> I dug into this a bit and it all seems quite broken:
>>>>
>>>> - PCI bus configuration does not work in gpio_ich6_pinctrl_init(). I
>>>> will send a patch for this
>>>> - gpio_ich6_get_base() returns a 16-bit word but function is also used
>>>> to read the memory address which holds a 32-bit word
>>>> - Intel's hardware won't let you read the status of an output!
>>>>
>>>> The last point means that _gpio_ich6_pinctrl_cfg_pin cannot work. We
>>>> need to mirror the lvl register in order to be able to read it.
>>>>
>>>> I confirmed that with the 'correct' value in the lvl registers both
>>>> USB ports work.
>>>
>>> I'm currently struggling with the USB EHCI ports on my custom Bay
>>> Trail x86 board. With the current U-Boot, cloned from the MinnowMAX,
>>> only some of the USB EHCI ports are enabled / available. Here
>>> the "usb tree" output with 3 USB keys installed:
>>>
>>> => usb tree
>>> USB device tree:
>>>    1  Hub (480 Mb/s, 0mA)
>>>    |  u-boot EHCI Host Controller
>>>    |
>>>    +-2  Hub (480 Mb/s, 0mA)
>>>      |
>>>      +-3  Hub (480 Mb/s, 100mA)
>>>      | |
>>>      | +-4  Hub (12 Mb/s, 100mA)
>>>      |
>>>      +-5  Mass Storage (480 Mb/s, 200mA)
>>>           JetFlash Mass Storage Device 3281440601
>>>
>>> When I first start the original (AMI) BIOS on this custom board,
>>> and then reboot into U-Boot (without a power-cycle), I see this
>>> configuration:
>>>
>>> => usb tree
>>> USB device tree:
>>>    1  Hub (480 Mb/s, 0mA)
>>>    |  u-boot EHCI Host Controller
>>>    |
>>>    +-2  Hub (480 Mb/s, 0mA)
>>>      |
>>>      +-3  Hub (480 Mb/s, 100mA)
>>>      | |
>>>      | +-4  Hub (12 Mb/s, 100mA)
>>>      |
>>>      +-5  Hub (480 Mb/s, 0mA)
>>>      | |
>>>      | +-6  Mass Storage (480 Mb/s, 200mA)
>>>      | |    Kingston DataTraveler 2.0 50E549C688C4BE7189942766
>>>      | |
>>>      | +-7  Mass Storage (480 Mb/s, 98mA)
>>>      |      USBest Technology USB Mass Storage Device 09092207fbf0c4
>>>      |
>>>      +-8  Mass Storage (480 Mb/s, 200mA)
>>>           JetFlash Mass Storage Device 3281440601
>>>
>>> So now all 3 USB sticks are detected.
>>>
>>> It doesn't seem to be a problem with missing USB power switch
>>> enabling via some GPIOs. I've checked the schematics and all ports
>>> should have power enabled.
>>>
>>> Do you have any quick ideas, what might be missing to enable all
>>> 4 EHCI ports on Bay Trail? There seems to be a per-port disable
>>> feature which might be involved. I'm still pretty new to x86, and
>>> I'm struggling with finding the correct datasheet for this. So any
>>> hints are really appreciated.
>>
>> It might be worth checking the pci bus device list in both cases.
>> Perhaps one of the USB ports is disabled?
>
> IIUTC, its only one PCI device, that handles all EHCI USB 2.0 ports.
> In both cases its this output:
>
> => pci
> Scanning PCI devices on bus 0
> BusDevFun  VendorId   DeviceId   Device Class       Sub-Class
> _____________________________________________________________
> 00.1f.00   0x8086     0x0f1c     Bridge device           0x01
> 00.00.00   0x8086     0x0f00     Bridge device           0x00
> 00.02.00   0x8086     0x0f31     Display controller      0x00
> 00.11.00   0x8086     0x0f15     Base system peripheral  0x05
> 00.12.00   0x8086     0x0f16     Base system peripheral  0x05
> 00.13.00   0x8086     0x0f23     Mass storage controller 0x06
> 00.15.00   0x8086     0x0f28     Multimedia device       0x01
> 00.18.00   0x8086     0x0f40     Base system peripheral  0x01
> 00.18.01   0x8086     0x0f41     Serial bus controller   0x80
> 00.18.02   0x8086     0x0f42     Serial bus controller   0x80
> 00.18.03   0x8086     0x0f43     Serial bus controller   0x80
> 00.18.04   0x8086     0x0f44     Serial bus controller   0x80
> 00.18.05   0x8086     0x0f45     Serial bus controller   0x80
> 00.18.06   0x8086     0x0f46     Serial bus controller   0x80
> 00.18.07   0x8086     0x0f47     Serial bus controller   0x80
> 00.1a.00   0x8086     0x0f18     Cryptographic device    0x80
> 00.1c.00   0x8086     0x0f48     Bridge device           0x04
> 00.1c.03   0x8086     0x0f4e     Bridge device           0x04
> 00.1d.00   0x8086     0x0f34     Serial bus controller   0x03
> 00.1e.00   0x8086     0x0f06     Base system peripheral  0x01
> 00.1e.01   0x8086     0x0f08     Serial bus controller   0x80
> 00.1e.02   0x8086     0x0f09     Serial bus controller   0x80
> 00.1e.04   0x8086     0x0f0c     Simple comm. controller 0x80
> 00.1e.05   0x8086     0x0f0e     Serial bus controller   0x80
> 00.1f.03   0x8086     0x0f12     Serial bus controller   0x05
>
> Here 00.1d.00 is the EHCI controller. The "pci long" output
> is also identical. So its not that simple I'm afraid.
>
> The Intel Atom Processor Z3600 and Z3700 Series Datasheet Vol 1
> mentions in chapter "10.3.1 EHCI USB 2.0 Controller Features" on
> page 150:
>
> • Per port USB disable
>
> Perhaps this feature is biting me here. I'm wondering how this can
> be configured.

That sounds likely.

Also: xHCI and EHCI Port Mapping

suggests that you need to make sure the ports are being driven by EHCI
instead of XHCI.

It mentions USB2HCSEL but I cannot find that in the datasheet.

It does appear here though:

https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/chromeos-2013.04/src/soc/intel/baytrail/perf_power.c

See  IOSF_PORT_0x5a here:

https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/broadwell_fsp/src/lib/reg_script.c

So it looks like you need to set up this port, and perhaps some others
asper that file.

>
> Any further ideas are welcome.
>
> Thanks,
> Stefan
>

Regards,
Simon

Hi Simon,

On 09.03.2016 00:33, Simon Glass wrote:

<snip>

>>>> I'm currently struggling with the USB EHCI ports on my custom Bay
>>>> Trail x86 board. With the current U-Boot, cloned from the MinnowMAX,
>>>> only some of the USB EHCI ports are enabled / available. Here
>>>> the "usb tree" output with 3 USB keys installed:
>>>>
>>>> => usb tree
>>>> USB device tree:
>>>>     1  Hub (480 Mb/s, 0mA)
>>>>     |  u-boot EHCI Host Controller
>>>>     |
>>>>     +-2  Hub (480 Mb/s, 0mA)
>>>>       |
>>>>       +-3  Hub (480 Mb/s, 100mA)
>>>>       | |
>>>>       | +-4  Hub (12 Mb/s, 100mA)
>>>>       |
>>>>       +-5  Mass Storage (480 Mb/s, 200mA)
>>>>            JetFlash Mass Storage Device 3281440601
>>>>
>>>> When I first start the original (AMI) BIOS on this custom board,
>>>> and then reboot into U-Boot (without a power-cycle), I see this
>>>> configuration:
>>>>
>>>> => usb tree
>>>> USB device tree:
>>>>     1  Hub (480 Mb/s, 0mA)
>>>>     |  u-boot EHCI Host Controller
>>>>     |
>>>>     +-2  Hub (480 Mb/s, 0mA)
>>>>       |
>>>>       +-3  Hub (480 Mb/s, 100mA)
>>>>       | |
>>>>       | +-4  Hub (12 Mb/s, 100mA)
>>>>       |
>>>>       +-5  Hub (480 Mb/s, 0mA)
>>>>       | |
>>>>       | +-6  Mass Storage (480 Mb/s, 200mA)
>>>>       | |    Kingston DataTraveler 2.0 50E549C688C4BE7189942766
>>>>       | |
>>>>       | +-7  Mass Storage (480 Mb/s, 98mA)
>>>>       |      USBest Technology USB Mass Storage Device 09092207fbf0c4
>>>>       |
>>>>       +-8  Mass Storage (480 Mb/s, 200mA)
>>>>            JetFlash Mass Storage Device 3281440601
>>>>
>>>> So now all 3 USB sticks are detected.
>>>>
>>>> It doesn't seem to be a problem with missing USB power switch
>>>> enabling via some GPIOs. I've checked the schematics and all ports
>>>> should have power enabled.
>>>>
>>>> Do you have any quick ideas, what might be missing to enable all
>>>> 4 EHCI ports on Bay Trail? There seems to be a per-port disable
>>>> feature which might be involved. I'm still pretty new to x86, and
>>>> I'm struggling with finding the correct datasheet for this. So any
>>>> hints are really appreciated.
>>>
>>> It might be worth checking the pci bus device list in both cases.
>>> Perhaps one of the USB ports is disabled?
>>
>> IIUTC, its only one PCI device, that handles all EHCI USB 2.0 ports.
>> In both cases its this output:
>>
>> => pci
>> Scanning PCI devices on bus 0
>> BusDevFun  VendorId   DeviceId   Device Class       Sub-Class
>> _____________________________________________________________
>> 00.1f.00   0x8086     0x0f1c     Bridge device           0x01
>> 00.00.00   0x8086     0x0f00     Bridge device           0x00
>> 00.02.00   0x8086     0x0f31     Display controller      0x00
>> 00.11.00   0x8086     0x0f15     Base system peripheral  0x05
>> 00.12.00   0x8086     0x0f16     Base system peripheral  0x05
>> 00.13.00   0x8086     0x0f23     Mass storage controller 0x06
>> 00.15.00   0x8086     0x0f28     Multimedia device       0x01
>> 00.18.00   0x8086     0x0f40     Base system peripheral  0x01
>> 00.18.01   0x8086     0x0f41     Serial bus controller   0x80
>> 00.18.02   0x8086     0x0f42     Serial bus controller   0x80
>> 00.18.03   0x8086     0x0f43     Serial bus controller   0x80
>> 00.18.04   0x8086     0x0f44     Serial bus controller   0x80
>> 00.18.05   0x8086     0x0f45     Serial bus controller   0x80
>> 00.18.06   0x8086     0x0f46     Serial bus controller   0x80
>> 00.18.07   0x8086     0x0f47     Serial bus controller   0x80
>> 00.1a.00   0x8086     0x0f18     Cryptographic device    0x80
>> 00.1c.00   0x8086     0x0f48     Bridge device           0x04
>> 00.1c.03   0x8086     0x0f4e     Bridge device           0x04
>> 00.1d.00   0x8086     0x0f34     Serial bus controller   0x03
>> 00.1e.00   0x8086     0x0f06     Base system peripheral  0x01
>> 00.1e.01   0x8086     0x0f08     Serial bus controller   0x80
>> 00.1e.02   0x8086     0x0f09     Serial bus controller   0x80
>> 00.1e.04   0x8086     0x0f0c     Simple comm. controller 0x80
>> 00.1e.05   0x8086     0x0f0e     Serial bus controller   0x80
>> 00.1f.03   0x8086     0x0f12     Serial bus controller   0x05
>>
>> Here 00.1d.00 is the EHCI controller. The "pci long" output
>> is also identical. So its not that simple I'm afraid.
>>
>> The Intel Atom Processor Z3600 and Z3700 Series Datasheet Vol 1
>> mentions in chapter "10.3.1 EHCI USB 2.0 Controller Features" on
>> page 150:
>>
>> • Per port USB disable
>>
>> Perhaps this feature is biting me here. I'm wondering how this can
>> be configured.
> 
> That sounds likely.
> 
> Also: xHCI and EHCI Port Mapping
> 
> suggests that you need to make sure the ports are being driven by EHCI
> instead of XHCI.
> 
> It mentions USB2HCSEL but I cannot find that in the datasheet.

Same here.
 
> It does appear here though:
> 
> https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/chromeos-2013.04/src/soc/intel/baytrail/perf_power.c
> 
> See  IOSF_PORT_0x5a here:
> 
> https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/broadwell_fsp/src/lib/reg_script.c
> 
> So it looks like you need to set up this port, and perhaps some others
> asper that file.

I've looked into these coreboot files today. And ported parts of them
to U-Boot to run these configurations there as well. Unfortunately
without any (positive) effect. Some things I've tested are:

Configure 0x5a / 0xd0 (USB2HCSEL???) to different values. All
without effect.

Unfortunately this value can't be read-out. At least I read always
0 here. So I can't see, if the AMI BIOS version configures here
something different.

Then I've started looking into ehci.c:

https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/chromeos-2013.04/src/soc/intel/baytrail/ehci.c

EHCI_USB2PDO (per-port disable) looked promising here. And writing
0xff into this reg results in all ports disabled:

=> usb tree
USB device tree:
  1  Hub (480 Mb/s, 0mA)
  |  u-boot EHCI Host Controller 
  |
  +-2  Hub (480 Mb/s, 0mA)

So this register at least has some effect. But its initialized with
0 and writing 0 into it does not fix the problem with the missing
ports.

I also ported the PHY values from usb2_phy_init() without any
changes. The values here are the default values, as I can read
them back. Also the AMI BIOS does not change these values, I've
double checked this as well.

So I'm nearly out of ideas right now what else to configure / test
to get all ports running. One idea is that the xHCI controller also
needs some configuration for this port muxing. See:

https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/chromeos-2013.04/src/soc/intel/baytrail/xhci.c:

		/* USB3 SuperSpeed Enable */
		REG_PCI_WRITE32(XHCI_USB3PR, BYTM_USB3_PORT_MAP),
		/* USB2 Port Route to XHCI */
		REG_PCI_WRITE32(XHCI_USB2PR, BYTM_USB2_PORT_MAP),

and:

		/* Set USB2 Port Routing Mask */
		REG_PCI_WRITE32(XHCI_USB2PRM, BYTM_USB2_PORT_MAP),
		/* Set USB3 Port Routing Mask */
		REG_PCI_WRITE32(XHCI_USB3PRM, BYTM_USB3_PORT_MAP),
		/*
		 * Disable ports if requested
		 */
		/* Open per-port disable control override */
		REG_IO_RMW16(ACPI_BASE_ADDRESS + UPRWC, ~0, UPRWC_WR_EN),
		REG_PCI_WRITE32(XHCI_USB2PDO, config->usb2_port_disable_mask),
		REG_PCI_WRITE32(XHCI_USB3PDO, config->usb3_port_disable_mask),
		/* Close per-port disable control override */
		REG_IO_RMW16(ACPI_BASE_ADDRESS + UPRWC, ~UPRWC_WR_EN, 0),

But I can only either see the EHCI or the xHCI controller via
"pci". If I configure the FSP to enable xHCI (fsp,enable-xhci)
the EHCI PCI device is not listed. And without this DT property
the xHCI PCI device is missing. So I only have access to one
USB controller at the some time.

Any further ideas are really welcome! :)

BTW: Did you (or somebody else?) already start moving xHCI (PCI) to
DM yet? If yes, could you perhaps provide this version so that I
could continue with it.

Thanks,
Stefan

Hi Stefan,

On 9 March 2016 at 09:15, Stefan Roese <sr@denx.de> wrote:
>
> Hi Simon,
>
> On 09.03.2016 00:33, Simon Glass wrote:
>
> <snip>
>
> >>>> I'm currently struggling with the USB EHCI ports on my custom Bay
> >>>> Trail x86 board. With the current U-Boot, cloned from the MinnowMAX,
> >>>> only some of the USB EHCI ports are enabled / available. Here
> >>>> the "usb tree" output with 3 USB keys installed:
> >>>>
> >>>> => usb tree
> >>>> USB device tree:
> >>>>     1  Hub (480 Mb/s, 0mA)
> >>>>     |  u-boot EHCI Host Controller
> >>>>     |
> >>>>     +-2  Hub (480 Mb/s, 0mA)
> >>>>       |
> >>>>       +-3  Hub (480 Mb/s, 100mA)
> >>>>       | |
> >>>>       | +-4  Hub (12 Mb/s, 100mA)
> >>>>       |
> >>>>       +-5  Mass Storage (480 Mb/s, 200mA)
> >>>>            JetFlash Mass Storage Device 3281440601
> >>>>
> >>>> When I first start the original (AMI) BIOS on this custom board,
> >>>> and then reboot into U-Boot (without a power-cycle), I see this
> >>>> configuration:
> >>>>
> >>>> => usb tree
> >>>> USB device tree:
> >>>>     1  Hub (480 Mb/s, 0mA)
> >>>>     |  u-boot EHCI Host Controller
> >>>>     |
> >>>>     +-2  Hub (480 Mb/s, 0mA)
> >>>>       |
> >>>>       +-3  Hub (480 Mb/s, 100mA)
> >>>>       | |
> >>>>       | +-4  Hub (12 Mb/s, 100mA)
> >>>>       |
> >>>>       +-5  Hub (480 Mb/s, 0mA)
> >>>>       | |
> >>>>       | +-6  Mass Storage (480 Mb/s, 200mA)
> >>>>       | |    Kingston DataTraveler 2.0 50E549C688C4BE7189942766
> >>>>       | |
> >>>>       | +-7  Mass Storage (480 Mb/s, 98mA)
> >>>>       |      USBest Technology USB Mass Storage Device 09092207fbf0c4
> >>>>       |
> >>>>       +-8  Mass Storage (480 Mb/s, 200mA)
> >>>>            JetFlash Mass Storage Device 3281440601
> >>>>
> >>>> So now all 3 USB sticks are detected.
> >>>>
> >>>> It doesn't seem to be a problem with missing USB power switch
> >>>> enabling via some GPIOs. I've checked the schematics and all ports
> >>>> should have power enabled.
> >>>>
> >>>> Do you have any quick ideas, what might be missing to enable all
> >>>> 4 EHCI ports on Bay Trail? There seems to be a per-port disable
> >>>> feature which might be involved. I'm still pretty new to x86, and
> >>>> I'm struggling with finding the correct datasheet for this. So any
> >>>> hints are really appreciated.
> >>>
> >>> It might be worth checking the pci bus device list in both cases.
> >>> Perhaps one of the USB ports is disabled?
> >>
> >> IIUTC, its only one PCI device, that handles all EHCI USB 2.0 ports.
> >> In both cases its this output:
> >>
> >> => pci
> >> Scanning PCI devices on bus 0
> >> BusDevFun  VendorId   DeviceId   Device Class       Sub-Class
> >> _____________________________________________________________
> >> 00.1f.00   0x8086     0x0f1c     Bridge device           0x01
> >> 00.00.00   0x8086     0x0f00     Bridge device           0x00
> >> 00.02.00   0x8086     0x0f31     Display controller      0x00
> >> 00.11.00   0x8086     0x0f15     Base system peripheral  0x05
> >> 00.12.00   0x8086     0x0f16     Base system peripheral  0x05
> >> 00.13.00   0x8086     0x0f23     Mass storage controller 0x06
> >> 00.15.00   0x8086     0x0f28     Multimedia device       0x01
> >> 00.18.00   0x8086     0x0f40     Base system peripheral  0x01
> >> 00.18.01   0x8086     0x0f41     Serial bus controller   0x80
> >> 00.18.02   0x8086     0x0f42     Serial bus controller   0x80
> >> 00.18.03   0x8086     0x0f43     Serial bus controller   0x80
> >> 00.18.04   0x8086     0x0f44     Serial bus controller   0x80
> >> 00.18.05   0x8086     0x0f45     Serial bus controller   0x80
> >> 00.18.06   0x8086     0x0f46     Serial bus controller   0x80
> >> 00.18.07   0x8086     0x0f47     Serial bus controller   0x80
> >> 00.1a.00   0x8086     0x0f18     Cryptographic device    0x80
> >> 00.1c.00   0x8086     0x0f48     Bridge device           0x04
> >> 00.1c.03   0x8086     0x0f4e     Bridge device           0x04
> >> 00.1d.00   0x8086     0x0f34     Serial bus controller   0x03
> >> 00.1e.00   0x8086     0x0f06     Base system peripheral  0x01
> >> 00.1e.01   0x8086     0x0f08     Serial bus controller   0x80
> >> 00.1e.02   0x8086     0x0f09     Serial bus controller   0x80
> >> 00.1e.04   0x8086     0x0f0c     Simple comm. controller 0x80
> >> 00.1e.05   0x8086     0x0f0e     Serial bus controller   0x80
> >> 00.1f.03   0x8086     0x0f12     Serial bus controller   0x05
> >>
> >> Here 00.1d.00 is the EHCI controller. The "pci long" output
> >> is also identical. So its not that simple I'm afraid.
> >>
> >> The Intel Atom Processor Z3600 and Z3700 Series Datasheet Vol 1
> >> mentions in chapter "10.3.1 EHCI USB 2.0 Controller Features" on
> >> page 150:
> >>
> >> • Per port USB disable
> >>
> >> Perhaps this feature is biting me here. I'm wondering how this can
> >> be configured.
> >
> > That sounds likely.
> >
> > Also: xHCI and EHCI Port Mapping
> >
> > suggests that you need to make sure the ports are being driven by EHCI
> > instead of XHCI.
> >
> > It mentions USB2HCSEL but I cannot find that in the datasheet.
>
> Same here.
>
> > It does appear here though:
> >
> > https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/chromeos-2013.04/src/soc/intel/baytrail/perf_power.c
> >
> > See  IOSF_PORT_0x5a here:
> >
> > https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/broadwell_fsp/src/lib/reg_script.c
> >
> > So it looks like you need to set up this port, and perhaps some others
> > asper that file.
>
> I've looked into these coreboot files today. And ported parts of them
> to U-Boot to run these configurations there as well. Unfortunately
> without any (positive) effect. Some things I've tested are:
>
> Configure 0x5a / 0xd0 (USB2HCSEL???) to different values. All
> without effect.
>
> Unfortunately this value can't be read-out. At least I read always
> 0 here. So I can't see, if the AMI BIOS version configures here
> something different.

That's really odd, because it looks like this is a read/write
interface. Worth digging int I think, and trying to find docs.

>
> Then I've started looking into ehci.c:
>
> https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/chromeos-2013.04/src/soc/intel/baytrail/ehci.c
>
> EHCI_USB2PDO (per-port disable) looked promising here. And writing
> 0xff into this reg results in all ports disabled:
>
> => usb tree
> USB device tree:
>   1  Hub (480 Mb/s, 0mA)
>   |  u-boot EHCI Host Controller
>   |
>   +-2  Hub (480 Mb/s, 0mA)
>
> So this register at least has some effect. But its initialized with
> 0 and writing 0 into it does not fix the problem with the missing
> ports.
>
> I also ported the PHY values from usb2_phy_init() without any
> changes. The values here are the default values, as I can read
> them back. Also the AMI BIOS does not change these values, I've
> double checked this as well.

BTW is the AMI BIOS UEFI? If so, for now I suppose you could boot into
U-Boot from that, and deal with the problem later.

>
> So I'm nearly out of ideas right now what else to configure / test
> to get all ports running. One idea is that the xHCI controller also
> needs some configuration for this port muxing. See:
>
> https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/chromeos-2013.04/src/soc/intel/baytrail/xhci.c:
>
>                 /* USB3 SuperSpeed Enable */
>                 REG_PCI_WRITE32(XHCI_USB3PR, BYTM_USB3_PORT_MAP),
>                 /* USB2 Port Route to XHCI */
>                 REG_PCI_WRITE32(XHCI_USB2PR, BYTM_USB2_PORT_MAP),
>
> and:
>
>                 /* Set USB2 Port Routing Mask */
>                 REG_PCI_WRITE32(XHCI_USB2PRM, BYTM_USB2_PORT_MAP),
>                 /* Set USB3 Port Routing Mask */
>                 REG_PCI_WRITE32(XHCI_USB3PRM, BYTM_USB3_PORT_MAP),
>                 /*
>                  * Disable ports if requested
>                  */
>                 /* Open per-port disable control override */
>                 REG_IO_RMW16(ACPI_BASE_ADDRESS + UPRWC, ~0, UPRWC_WR_EN),
>                 REG_PCI_WRITE32(XHCI_USB2PDO, config->usb2_port_disable_mask),
>                 REG_PCI_WRITE32(XHCI_USB3PDO, config->usb3_port_disable_mask),
>                 /* Close per-port disable control override */
>                 REG_IO_RMW16(ACPI_BASE_ADDRESS + UPRWC, ~UPRWC_WR_EN, 0),
>
> But I can only either see the EHCI or the xHCI controller via
> "pci". If I configure the FSP to enable xHCI (fsp,enable-xhci)
> the EHCI PCI device is not listed. And without this DT property
> the xHCI PCI device is missing. So I only have access to one
> USB controller at the some time.
>
> Any further ideas are really welcome! :)

I'm pretty short on time this month otherwise I would love to look at
this. Can you post a patch that adds all the init code you have found
to baytrail?

>
> BTW: Did you (or somebody else?) already start moving xHCI (PCI) to
> DM yet? If yes, could you perhaps provide this version so that I
> could continue with it.

Yes, see u-boot-x86/samus-working.

>
> Thanks,
> Stefan
>

Regards,
Simon

Hi Simon,

On 09.03.2016 18:11, Simon Glass wrote:
> On 9 March 2016 at 09:15, Stefan Roese <sr@denx.de> wrote:
>>
>> Hi Simon,
>>
>> On 09.03.2016 00:33, Simon Glass wrote:
>>
>> <snip>
>>
>>>>>> I'm currently struggling with the USB EHCI ports on my custom Bay
>>>>>> Trail x86 board. With the current U-Boot, cloned from the MinnowMAX,
>>>>>> only some of the USB EHCI ports are enabled / available. Here
>>>>>> the "usb tree" output with 3 USB keys installed:
>>>>>>
>>>>>> => usb tree
>>>>>> USB device tree:
>>>>>>      1  Hub (480 Mb/s, 0mA)
>>>>>>      |  u-boot EHCI Host Controller
>>>>>>      |
>>>>>>      +-2  Hub (480 Mb/s, 0mA)
>>>>>>        |
>>>>>>        +-3  Hub (480 Mb/s, 100mA)
>>>>>>        | |
>>>>>>        | +-4  Hub (12 Mb/s, 100mA)
>>>>>>        |
>>>>>>        +-5  Mass Storage (480 Mb/s, 200mA)
>>>>>>             JetFlash Mass Storage Device 3281440601
>>>>>>
>>>>>> When I first start the original (AMI) BIOS on this custom board,
>>>>>> and then reboot into U-Boot (without a power-cycle), I see this
>>>>>> configuration:
>>>>>>
>>>>>> => usb tree
>>>>>> USB device tree:
>>>>>>      1  Hub (480 Mb/s, 0mA)
>>>>>>      |  u-boot EHCI Host Controller
>>>>>>      |
>>>>>>      +-2  Hub (480 Mb/s, 0mA)
>>>>>>        |
>>>>>>        +-3  Hub (480 Mb/s, 100mA)
>>>>>>        | |
>>>>>>        | +-4  Hub (12 Mb/s, 100mA)
>>>>>>        |
>>>>>>        +-5  Hub (480 Mb/s, 0mA)
>>>>>>        | |
>>>>>>        | +-6  Mass Storage (480 Mb/s, 200mA)
>>>>>>        | |    Kingston DataTraveler 2.0 50E549C688C4BE7189942766
>>>>>>        | |
>>>>>>        | +-7  Mass Storage (480 Mb/s, 98mA)
>>>>>>        |      USBest Technology USB Mass Storage Device 09092207fbf0c4
>>>>>>        |
>>>>>>        +-8  Mass Storage (480 Mb/s, 200mA)
>>>>>>             JetFlash Mass Storage Device 3281440601
>>>>>>
>>>>>> So now all 3 USB sticks are detected.
>>>>>>
>>>>>> It doesn't seem to be a problem with missing USB power switch
>>>>>> enabling via some GPIOs. I've checked the schematics and all ports
>>>>>> should have power enabled.
>>>>>>
>>>>>> Do you have any quick ideas, what might be missing to enable all
>>>>>> 4 EHCI ports on Bay Trail? There seems to be a per-port disable
>>>>>> feature which might be involved. I'm still pretty new to x86, and
>>>>>> I'm struggling with finding the correct datasheet for this. So any
>>>>>> hints are really appreciated.
>>>>>
>>>>> It might be worth checking the pci bus device list in both cases.
>>>>> Perhaps one of the USB ports is disabled?
>>>>
>>>> IIUTC, its only one PCI device, that handles all EHCI USB 2.0 ports.
>>>> In both cases its this output:
>>>>
>>>> => pci
>>>> Scanning PCI devices on bus 0
>>>> BusDevFun  VendorId   DeviceId   Device Class       Sub-Class
>>>> _____________________________________________________________
>>>> 00.1f.00   0x8086     0x0f1c     Bridge device           0x01
>>>> 00.00.00   0x8086     0x0f00     Bridge device           0x00
>>>> 00.02.00   0x8086     0x0f31     Display controller      0x00
>>>> 00.11.00   0x8086     0x0f15     Base system peripheral  0x05
>>>> 00.12.00   0x8086     0x0f16     Base system peripheral  0x05
>>>> 00.13.00   0x8086     0x0f23     Mass storage controller 0x06
>>>> 00.15.00   0x8086     0x0f28     Multimedia device       0x01
>>>> 00.18.00   0x8086     0x0f40     Base system peripheral  0x01
>>>> 00.18.01   0x8086     0x0f41     Serial bus controller   0x80
>>>> 00.18.02   0x8086     0x0f42     Serial bus controller   0x80
>>>> 00.18.03   0x8086     0x0f43     Serial bus controller   0x80
>>>> 00.18.04   0x8086     0x0f44     Serial bus controller   0x80
>>>> 00.18.05   0x8086     0x0f45     Serial bus controller   0x80
>>>> 00.18.06   0x8086     0x0f46     Serial bus controller   0x80
>>>> 00.18.07   0x8086     0x0f47     Serial bus controller   0x80
>>>> 00.1a.00   0x8086     0x0f18     Cryptographic device    0x80
>>>> 00.1c.00   0x8086     0x0f48     Bridge device           0x04
>>>> 00.1c.03   0x8086     0x0f4e     Bridge device           0x04
>>>> 00.1d.00   0x8086     0x0f34     Serial bus controller   0x03
>>>> 00.1e.00   0x8086     0x0f06     Base system peripheral  0x01
>>>> 00.1e.01   0x8086     0x0f08     Serial bus controller   0x80
>>>> 00.1e.02   0x8086     0x0f09     Serial bus controller   0x80
>>>> 00.1e.04   0x8086     0x0f0c     Simple comm. controller 0x80
>>>> 00.1e.05   0x8086     0x0f0e     Serial bus controller   0x80
>>>> 00.1f.03   0x8086     0x0f12     Serial bus controller   0x05
>>>>
>>>> Here 00.1d.00 is the EHCI controller. The "pci long" output
>>>> is also identical. So its not that simple I'm afraid.
>>>>
>>>> The Intel Atom Processor Z3600 and Z3700 Series Datasheet Vol 1
>>>> mentions in chapter "10.3.1 EHCI USB 2.0 Controller Features" on
>>>> page 150:
>>>>
>>>> • Per port USB disable
>>>>
>>>> Perhaps this feature is biting me here. I'm wondering how this can
>>>> be configured.
>>>
>>> That sounds likely.
>>>
>>> Also: xHCI and EHCI Port Mapping
>>>
>>> suggests that you need to make sure the ports are being driven by EHCI
>>> instead of XHCI.
>>>
>>> It mentions USB2HCSEL but I cannot find that in the datasheet.
>>
>> Same here.
>>
>>> It does appear here though:
>>>
>>> https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/chromeos-2013.04/src/soc/intel/baytrail/perf_power.c
>>>
>>> See  IOSF_PORT_0x5a here:
>>>
>>> https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/broadwell_fsp/src/lib/reg_script.c
>>>
>>> So it looks like you need to set up this port, and perhaps some others
>>> asper that file.
>>
>> I've looked into these coreboot files today. And ported parts of them
>> to U-Boot to run these configurations there as well. Unfortunately
>> without any (positive) effect. Some things I've tested are:
>>
>> Configure 0x5a / 0xd0 (USB2HCSEL???) to different values. All
>> without effect.
>>
>> Unfortunately this value can't be read-out. At least I read always
>> 0 here. So I can't see, if the AMI BIOS version configures here
>> something different.
>
> That's really odd, because it looks like this is a read/write
> interface. Worth digging int I think, and trying to find docs.

I've really tried to find some docs here. But all I can find on the
net are the links to the coreboot source.

I've also printed all 0x5a registers, well not all but from 0x00 to
0x200. And all of them are read as 0. Yes, this is odd but I can't
see that I'm doing something wrong here while reading those values.

>>
>> Then I've started looking into ehci.c:
>>
>> https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/chromeos-2013.04/src/soc/intel/baytrail/ehci.c
>>
>> EHCI_USB2PDO (per-port disable) looked promising here. And writing
>> 0xff into this reg results in all ports disabled:
>>
>> => usb tree
>> USB device tree:
>>    1  Hub (480 Mb/s, 0mA)
>>    |  u-boot EHCI Host Controller
>>    |
>>    +-2  Hub (480 Mb/s, 0mA)
>>
>> So this register at least has some effect. But its initialized with
>> 0 and writing 0 into it does not fix the problem with the missing
>> ports.
>>
>> I also ported the PHY values from usb2_phy_init() without any
>> changes. The values here are the default values, as I can read
>> them back. Also the AMI BIOS does not change these values, I've
>> double checked this as well.
>
> BTW is the AMI BIOS UEFI?

I think so - I need to check to be 100% sure though.

> If so, for now I suppose you could boot into
> U-Boot from that, and deal with the problem later.

Interesting idea. Right now I'm booting into the AMI BIOS once, and then
only doing reset's into U-Boot (I can toggle the SPI NOR chip via
a DIP switch, which is quite handy).

>>
>> So I'm nearly out of ideas right now what else to configure / test
>> to get all ports running. One idea is that the xHCI controller also
>> needs some configuration for this port muxing. See:
>>
>> https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/chromeos-2013.04/src/soc/intel/baytrail/xhci.c:
>>
>>                  /* USB3 SuperSpeed Enable */
>>                  REG_PCI_WRITE32(XHCI_USB3PR, BYTM_USB3_PORT_MAP),
>>                  /* USB2 Port Route to XHCI */
>>                  REG_PCI_WRITE32(XHCI_USB2PR, BYTM_USB2_PORT_MAP),
>>
>> and:
>>
>>                  /* Set USB2 Port Routing Mask */
>>                  REG_PCI_WRITE32(XHCI_USB2PRM, BYTM_USB2_PORT_MAP),
>>                  /* Set USB3 Port Routing Mask */
>>                  REG_PCI_WRITE32(XHCI_USB3PRM, BYTM_USB3_PORT_MAP),
>>                  /*
>>                   * Disable ports if requested
>>                   */
>>                  /* Open per-port disable control override */
>>                  REG_IO_RMW16(ACPI_BASE_ADDRESS + UPRWC, ~0, UPRWC_WR_EN),
>>                  REG_PCI_WRITE32(XHCI_USB2PDO, config->usb2_port_disable_mask),
>>                  REG_PCI_WRITE32(XHCI_USB3PDO, config->usb3_port_disable_mask),
>>                  /* Close per-port disable control override */
>>                  REG_IO_RMW16(ACPI_BASE_ADDRESS + UPRWC, ~UPRWC_WR_EN, 0),
>>
>> But I can only either see the EHCI or the xHCI controller via
>> "pci". If I configure the FSP to enable xHCI (fsp,enable-xhci)
>> the EHCI PCI device is not listed. And without this DT property
>> the xHCI PCI device is missing. So I only have access to one
>> USB controller at the some time.
>>
>> Any further ideas are really welcome! :)
>
> I'm pretty short on time this month otherwise I would love to look at
> this.

That would be great, thanks!

> Can you post a patch that adds all the init code you have found
> to baytrail?

I need to clean this mess up a bit before I can post something of
this. And I've used the last few days to implement the USB scanning
enhancements, as you will have noticed in your inbox. :)

I'll definitely come back to your offer beginning of next week
and will post this coreboot register access stuff I've added to
my platform code for testing.

>>
>> BTW: Did you (or somebody else?) already start moving xHCI (PCI) to
>> DM yet? If yes, could you perhaps provide this version so that I
>> could continue with it.
>
> Yes, see u-boot-x86/samus-working.

Thanks. I'll probably look into this next week.

Thanks,
Stefan

Hi Stefan,

On 11 March 2016 at 09:28, Stefan Roese <sr@denx.de> wrote:
> Hi Simon,
>
>
> On 09.03.2016 18:11, Simon Glass wrote:
>>
>> On 9 March 2016 at 09:15, Stefan Roese <sr@denx.de> wrote:
>>>
>>>
>>> Hi Simon,
>>>
>>> On 09.03.2016 00:33, Simon Glass wrote:
>>>
>>> <snip>
>>>
>>>>>>> I'm currently struggling with the USB EHCI ports on my custom Bay
>>>>>>> Trail x86 board. With the current U-Boot, cloned from the MinnowMAX,
>>>>>>> only some of the USB EHCI ports are enabled / available. Here
>>>>>>> the "usb tree" output with 3 USB keys installed:
>>>>>>>
>>>>>>> => usb tree
>>>>>>> USB device tree:
>>>>>>>      1  Hub (480 Mb/s, 0mA)
>>>>>>>      |  u-boot EHCI Host Controller
>>>>>>>      |
>>>>>>>      +-2  Hub (480 Mb/s, 0mA)
>>>>>>>        |
>>>>>>>        +-3  Hub (480 Mb/s, 100mA)
>>>>>>>        | |
>>>>>>>        | +-4  Hub (12 Mb/s, 100mA)
>>>>>>>        |
>>>>>>>        +-5  Mass Storage (480 Mb/s, 200mA)
>>>>>>>             JetFlash Mass Storage Device 3281440601
>>>>>>>
>>>>>>> When I first start the original (AMI) BIOS on this custom board,
>>>>>>> and then reboot into U-Boot (without a power-cycle), I see this
>>>>>>> configuration:
>>>>>>>
>>>>>>> => usb tree
>>>>>>> USB device tree:
>>>>>>>      1  Hub (480 Mb/s, 0mA)
>>>>>>>      |  u-boot EHCI Host Controller
>>>>>>>      |
>>>>>>>      +-2  Hub (480 Mb/s, 0mA)
>>>>>>>        |
>>>>>>>        +-3  Hub (480 Mb/s, 100mA)
>>>>>>>        | |
>>>>>>>        | +-4  Hub (12 Mb/s, 100mA)
>>>>>>>        |
>>>>>>>        +-5  Hub (480 Mb/s, 0mA)
>>>>>>>        | |
>>>>>>>        | +-6  Mass Storage (480 Mb/s, 200mA)
>>>>>>>        | |    Kingston DataTraveler 2.0 50E549C688C4BE7189942766
>>>>>>>        | |
>>>>>>>        | +-7  Mass Storage (480 Mb/s, 98mA)
>>>>>>>        |      USBest Technology USB Mass Storage Device
>>>>>>> 09092207fbf0c4
>>>>>>>        |
>>>>>>>        +-8  Mass Storage (480 Mb/s, 200mA)
>>>>>>>             JetFlash Mass Storage Device 3281440601
>>>>>>>
>>>>>>> So now all 3 USB sticks are detected.
>>>>>>>
>>>>>>> It doesn't seem to be a problem with missing USB power switch
>>>>>>> enabling via some GPIOs. I've checked the schematics and all ports
>>>>>>> should have power enabled.
>>>>>>>
>>>>>>> Do you have any quick ideas, what might be missing to enable all
>>>>>>> 4 EHCI ports on Bay Trail? There seems to be a per-port disable
>>>>>>> feature which might be involved. I'm still pretty new to x86, and
>>>>>>> I'm struggling with finding the correct datasheet for this. So any
>>>>>>> hints are really appreciated.
>>>>>>
>>>>>>
>>>>>> It might be worth checking the pci bus device list in both cases.
>>>>>> Perhaps one of the USB ports is disabled?
>>>>>
>>>>>
>>>>> IIUTC, its only one PCI device, that handles all EHCI USB 2.0 ports.
>>>>> In both cases its this output:
>>>>>
>>>>> => pci
>>>>> Scanning PCI devices on bus 0
>>>>> BusDevFun  VendorId   DeviceId   Device Class       Sub-Class
>>>>> _____________________________________________________________
>>>>> 00.1f.00   0x8086     0x0f1c     Bridge device           0x01
>>>>> 00.00.00   0x8086     0x0f00     Bridge device           0x00
>>>>> 00.02.00   0x8086     0x0f31     Display controller      0x00
>>>>> 00.11.00   0x8086     0x0f15     Base system peripheral  0x05
>>>>> 00.12.00   0x8086     0x0f16     Base system peripheral  0x05
>>>>> 00.13.00   0x8086     0x0f23     Mass storage controller 0x06
>>>>> 00.15.00   0x8086     0x0f28     Multimedia device       0x01
>>>>> 00.18.00   0x8086     0x0f40     Base system peripheral  0x01
>>>>> 00.18.01   0x8086     0x0f41     Serial bus controller   0x80
>>>>> 00.18.02   0x8086     0x0f42     Serial bus controller   0x80
>>>>> 00.18.03   0x8086     0x0f43     Serial bus controller   0x80
>>>>> 00.18.04   0x8086     0x0f44     Serial bus controller   0x80
>>>>> 00.18.05   0x8086     0x0f45     Serial bus controller   0x80
>>>>> 00.18.06   0x8086     0x0f46     Serial bus controller   0x80
>>>>> 00.18.07   0x8086     0x0f47     Serial bus controller   0x80
>>>>> 00.1a.00   0x8086     0x0f18     Cryptographic device    0x80
>>>>> 00.1c.00   0x8086     0x0f48     Bridge device           0x04
>>>>> 00.1c.03   0x8086     0x0f4e     Bridge device           0x04
>>>>> 00.1d.00   0x8086     0x0f34     Serial bus controller   0x03
>>>>> 00.1e.00   0x8086     0x0f06     Base system peripheral  0x01
>>>>> 00.1e.01   0x8086     0x0f08     Serial bus controller   0x80
>>>>> 00.1e.02   0x8086     0x0f09     Serial bus controller   0x80
>>>>> 00.1e.04   0x8086     0x0f0c     Simple comm. controller 0x80
>>>>> 00.1e.05   0x8086     0x0f0e     Serial bus controller   0x80
>>>>> 00.1f.03   0x8086     0x0f12     Serial bus controller   0x05
>>>>>
>>>>> Here 00.1d.00 is the EHCI controller. The "pci long" output
>>>>> is also identical. So its not that simple I'm afraid.
>>>>>
>>>>> The Intel Atom Processor Z3600 and Z3700 Series Datasheet Vol 1
>>>>> mentions in chapter "10.3.1 EHCI USB 2.0 Controller Features" on
>>>>> page 150:
>>>>>
>>>>> • Per port USB disable
>>>>>
>>>>> Perhaps this feature is biting me here. I'm wondering how this can
>>>>> be configured.
>>>>
>>>>
>>>> That sounds likely.
>>>>
>>>> Also: xHCI and EHCI Port Mapping
>>>>
>>>> suggests that you need to make sure the ports are being driven by EHCI
>>>> instead of XHCI.
>>>>
>>>> It mentions USB2HCSEL but I cannot find that in the datasheet.
>>>
>>>
>>> Same here.
>>>
>>>> It does appear here though:
>>>>
>>>>
>>>> https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/chromeos-2013.04/src/soc/intel/baytrail/perf_power.c
>>>>
>>>> See  IOSF_PORT_0x5a here:
>>>>
>>>>
>>>> https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/broadwell_fsp/src/lib/reg_script.c
>>>>
>>>> So it looks like you need to set up this port, and perhaps some others
>>>> asper that file.
>>>
>>>
>>> I've looked into these coreboot files today. And ported parts of them
>>> to U-Boot to run these configurations there as well. Unfortunately
>>> without any (positive) effect. Some things I've tested are:
>>>
>>> Configure 0x5a / 0xd0 (USB2HCSEL???) to different values. All
>>> without effect.
>>>
>>> Unfortunately this value can't be read-out. At least I read always
>>> 0 here. So I can't see, if the AMI BIOS version configures here
>>> something different.
>>
>>
>> That's really odd, because it looks like this is a read/write
>> interface. Worth digging int I think, and trying to find docs.
>
>
> I've really tried to find some docs here. But all I can find on the
> net are the links to the coreboot source.
>
> I've also printed all 0x5a registers, well not all but from 0x00 to
> 0x200. And all of them are read as 0. Yes, this is odd but I can't
> see that I'm doing something wrong here while reading those values.
>
>>>
>>> Then I've started looking into ehci.c:
>>>
>>>
>>> https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/chromeos-2013.04/src/soc/intel/baytrail/ehci.c
>>>
>>> EHCI_USB2PDO (per-port disable) looked promising here. And writing
>>> 0xff into this reg results in all ports disabled:
>>>
>>> => usb tree
>>> USB device tree:
>>>    1  Hub (480 Mb/s, 0mA)
>>>    |  u-boot EHCI Host Controller
>>>    |
>>>    +-2  Hub (480 Mb/s, 0mA)
>>>
>>> So this register at least has some effect. But its initialized with
>>> 0 and writing 0 into it does not fix the problem with the missing
>>> ports.
>>>
>>> I also ported the PHY values from usb2_phy_init() without any
>>> changes. The values here are the default values, as I can read
>>> them back. Also the AMI BIOS does not change these values, I've
>>> double checked this as well.
>>
>>
>> BTW is the AMI BIOS UEFI?
>
>
> I think so - I need to check to be 100% sure though.
>
>> If so, for now I suppose you could boot into
>> U-Boot from that, and deal with the problem later.
>
>
> Interesting idea. Right now I'm booting into the AMI BIOS once, and then
> only doing reset's into U-Boot (I can toggle the SPI NOR chip via
> a DIP switch, which is quite handy).
>
>
>>>
>>> So I'm nearly out of ideas right now what else to configure / test
>>> to get all ports running. One idea is that the xHCI controller also
>>> needs some configuration for this port muxing. See:
>>>
>>>
>>> https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/chromeos-2013.04/src/soc/intel/baytrail/xhci.c:
>>>
>>>                  /* USB3 SuperSpeed Enable */
>>>                  REG_PCI_WRITE32(XHCI_USB3PR, BYTM_USB3_PORT_MAP),
>>>                  /* USB2 Port Route to XHCI */
>>>                  REG_PCI_WRITE32(XHCI_USB2PR, BYTM_USB2_PORT_MAP),
>>>
>>> and:
>>>
>>>                  /* Set USB2 Port Routing Mask */
>>>                  REG_PCI_WRITE32(XHCI_USB2PRM, BYTM_USB2_PORT_MAP),
>>>                  /* Set USB3 Port Routing Mask */
>>>                  REG_PCI_WRITE32(XHCI_USB3PRM, BYTM_USB3_PORT_MAP),
>>>                  /*
>>>                   * Disable ports if requested
>>>                   */
>>>                  /* Open per-port disable control override */
>>>                  REG_IO_RMW16(ACPI_BASE_ADDRESS + UPRWC, ~0,
>>> UPRWC_WR_EN),
>>>                  REG_PCI_WRITE32(XHCI_USB2PDO,
>>> config->usb2_port_disable_mask),
>>>                  REG_PCI_WRITE32(XHCI_USB3PDO,
>>> config->usb3_port_disable_mask),
>>>                  /* Close per-port disable control override */
>>>                  REG_IO_RMW16(ACPI_BASE_ADDRESS + UPRWC, ~UPRWC_WR_EN,
>>> 0),
>>>
>>> But I can only either see the EHCI or the xHCI controller via
>>> "pci". If I configure the FSP to enable xHCI (fsp,enable-xhci)
>>> the EHCI PCI device is not listed. And without this DT property
>>> the xHCI PCI device is missing. So I only have access to one
>>> USB controller at the some time.
>>>
>>> Any further ideas are really welcome! :)
>>
>>
>> I'm pretty short on time this month otherwise I would love to look at
>> this.
>
>
> That would be great, thanks!
>
>> Can you post a patch that adds all the init code you have found
>> to baytrail?
>
>
> I need to clean this mess up a bit before I can post something of
> this. And I've used the last few days to implement the USB scanning
> enhancements, as you will have noticed in your inbox. :)
>
> I'll definitely come back to your offer beginning of next week
> and will post this coreboot register access stuff I've added to
> my platform code for testing.

Actually I was saying that I am short on time, not that I can look at
ti soon :-)  I'm pretty tied up with travel etc. for the next 3 weeks,
sorry.

>
>>>
>>> BTW: Did you (or somebody else?) already start moving xHCI (PCI) to
>>> DM yet? If yes, could you perhaps provide this version so that I
>>> could continue with it.
>>
>>
>> Yes, see u-boot-x86/samus-working.
>
>
> Thanks. I'll probably look into this next week.
>
> Thanks,
> Stefan
>

Regards,
Simon