From patchwork Wed Aug 27 14:34:32 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 383467 X-Patchwork-Delegate: twarren@nvidia.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 10564140093 for ; Thu, 28 Aug 2014 00:34:52 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 63765A74C2; Wed, 27 Aug 2014 16:34:50 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id CHu+SfyP6w51; Wed, 27 Aug 2014 16:34:48 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 9DE0BA74E6; Wed, 27 Aug 2014 16:34:47 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 8AFF2A74C2 for ; Wed, 27 Aug 2014 16:34:42 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id iLQ6kqpVDKVm for ; Wed, 27 Aug 2014 16:34:39 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-wg0-f52.google.com (mail-wg0-f52.google.com [74.125.82.52]) by theia.denx.de (Postfix) with ESMTPS id 7A0A5A74BF for ; Wed, 27 Aug 2014 16:34:35 +0200 (CEST) Received: by mail-wg0-f52.google.com with SMTP id a1so313204wgh.11 for ; Wed, 27 Aug 2014 07:34:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=date:from:to:cc:subject:message-id:references:mime-version :content-type:content-disposition:in-reply-to:user-agent; bh=XpoQDv61Cray6Gm4eGVTv3aX5BNI6ivvAUNIpSBB0uw=; b=b+6B2fEy7GZY4yYhzs6S2Q7d3/4X6DF+kzC0zxwgFMb2iKCU0K452uTuxrrhg0wkGC gdgsaXmRBc7vMuKE/TaWVqNPFMfK1Qaq4Y9xYCk2PytqwniMRk6nAVXr5JLcFOYuK198 3mrH15l0ZwxB7d34cTIc7k8Toxc529Caog0o1p0di8Bsgz5UcjKfJ+YG9yfTHOIPKVbg jVCNY4DfhyeIsfVI+CfMxXDNa+u7HYXA0Xdnaru9jJA/eww08ECA1U8OIu3lwMQjm/lZ oW3HYnD0NRxBdrISrTNtBRHYXJc8nAVnf3eqlSuByoqAXvWPcVaSYjeu3Hm4nMXWP/Ul /tIA== X-Received: by 10.180.38.2 with SMTP id c2mr27871189wik.24.1409150075028; Wed, 27 Aug 2014 07:34:35 -0700 (PDT) Received: from localhost (port-33682.pppoe.wtnet.de. [46.59.182.103]) by mx.google.com with ESMTPSA id p1sm265102wjy.22.2014.08.27.07.34.33 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 27 Aug 2014 07:34:34 -0700 (PDT) Date: Wed, 27 Aug 2014 16:34:32 +0200 From: Thierry Reding To: Tuomas Tynkkynen Message-ID: <20140827143431.GD32243@ulmo> References: <1408346196-30419-1-git-send-email-thierry.reding@gmail.com> <1408346196-30419-24-git-send-email-thierry.reding@gmail.com> <53FC839A.7030108@nvidia.com> <20140827132800.GA32243@ulmo> MIME-Version: 1.0 In-Reply-To: <20140827132800.GA32243@ulmo> User-Agent: Mutt/1.5.23 (2014-03-12) Cc: u-boot@lists.denx.de, Stephen Warren , Tom Warren Subject: Re: [U-Boot] [PATCH 23/23] ARM: tegra: Enable PCIe on Jetson TK1 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de On Wed, Aug 27, 2014 at 03:28:06PM +0200, Thierry Reding wrote: > On Tue, Aug 26, 2014 at 03:54:50PM +0300, Tuomas Tynkkynen wrote: > > On 18/08/14 10:16, Thierry Reding wrote: > > [...] > > > +static int as3722_gpio_direction_output(u8 gpio, u8 level) > > > +{ > > > + u8 value; > > > + int err; > > > + > > > + if (gpio > 7) > > > + return -EINVAL; > > > + > > > + if (level == 0) > > > + value = AS3722_GPIO_CONTROL_MODE_OUTPUT_VDDL; > > > + else > > > + value = AS3722_GPIO_CONTROL_MODE_OUTPUT_VDDH; > > > + > > > + err = as3722_write(AS3722_GPIO_CONTROL(gpio), value); > > > + if (err) { > > > + error("as3722: failed to configure GPIO#%u as output: %d\n", > > > + gpio, err); > > > + return err; > > > + } > > > + > > > + err = as3722_gpio_set(gpio, level); > > > + if (err < 0) { > > > + error("as3722: failed to set GPIO#%u high: %d\n", gpio, err); > > > + return err; > > > + } > > > + > > > + return 0; > > > +} > > > > This function doesn't work correctly if the GPIO was originally configured > > as inverted and low, which GPIO#2 seems to be. > > (as3722_read(AS3722_GPIO_CONTROL(2), &value) returns value == 0x87)... > > That should be equivalent to what we're setting but is a somewhat weird > default. I guess the fact that we're inverting it and then changing the > value to high in separate transactions makes the output flip twice. > > > > + > > > +int tegra_pcie_board_init(void) > > > +{ > > [...] > > > + > > > + err = as3722_gpio_direction_output(2, 1); > > > + if (err < 0) { > > > + error("as3722: failed to set GPIO#2 high: %d\n", err); > > > + return err; > > > + } > > [...] > > > > On my board, this call results in UART corruption, like this: > > > > tegra-pcie: non-prefetchable memory: 0x13000000-0x20000000 > > tegra-pcie: prefetchable memory: 0x20000000-0x40000000 > > ¥É½¥¹½bªÍ¥¹b2x1, 1x1 configuration > > ¹Í5Rþtegra-pcie: probing port 1, using 1 lanes > > > > Likely because GPIO#2 controls the +3.3V_LP0 rail, which powers the UART > > level shifters. Commenting the function call out fixes the corruption and > > PCI-E still works fine. > > If I add a udelay(500) after the above I'm not able to reproduce the > UART breakage anymore. But I guess making the AS3722 GPIO code smarter > would be helpful. In the kernel this is done by checking the invert bit > and then setting the value accordingly. I suppose the same could be done > for the mode bits. I'll see if I can work up a patch. How about this: diff --git a/drivers/power/as3722.c b/drivers/power/as3722.c index 59d1bf1b50b0..393dc8608d07 100644 --- a/drivers/power/as3722.c +++ b/drivers/power/as3722.c @@ -17,6 +17,7 @@ #define AS3722_GPIO_CONTROL(n) (0x08 + (n)) #define AS3722_GPIO_CONTROL_MODE_OUTPUT_VDDH (1 << 0) #define AS3722_GPIO_CONTROL_MODE_OUTPUT_VDDL (7 << 0) +#define AS3722_GPIO_CONTROL_MODE_MASK (7 << 0) #define AS3722_GPIO_CONTROL_INVERT (1 << 7) #define AS3722_LDO_VOLTAGE(n) (0x10 + (n)) #define AS3722_GPIO_SIGNAL_OUT 0x20 @@ -220,10 +221,21 @@ int as3722_gpio_direction_output(struct as3722 *pmic, unsigned int gpio, if (gpio > 7) return -EINVAL; + err = as3722_read(pmic, AS3722_GPIO_CONTROL(gpio), &value); + if (err < 0) { + error("failed to read GPIO#%u control register: %d", gpio, err); + return err; + } + + if (value & AS3722_GPIO_CONTROL_INVERT) + level = !level; + + value &= ~AS3722_GPIO_CONTROL_MODE_MASK; + if (level == 0) - value = AS3722_GPIO_CONTROL_MODE_OUTPUT_VDDL; + value |= AS3722_GPIO_CONTROL_MODE_OUTPUT_VDDL; else - value = AS3722_GPIO_CONTROL_MODE_OUTPUT_VDDH; + value |= AS3722_GPIO_CONTROL_MODE_OUTPUT_VDDH; err = as3722_write(pmic, AS3722_GPIO_CONTROL(gpio), value); if (err) {