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Wed, 15 Jan 2014 14:27:09 +0900 (KST) X-AuditID: cbfee691-b7efc6d0000039d3-ea-52d61c2d5859 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id CC.00.28157.D2C16D25; Wed, 15 Jan 2014 14:27:09 +0900 (KST) Received: from songinha-Samsung-DeskTop-System ([10.252.81.136]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MZF00FJ0GH9RI10@mmp2.samsung.com>; Wed, 15 Jan 2014 14:27:09 +0900 (KST) Date: Wed, 15 Jan 2014 14:27:59 +0900 From: Inha Song To: "u-boot.denx" Message-id: <20140115142759.66afd1ce@songinha-Samsung-DeskTop-System> X-Mailer: Claws Mail 3.8.0 (GTK+ 2.24.10; i686-pc-linux-gnu) MIME-version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprCIsWRmVeSWpSXmKPExsWyRsSkWFdX5lqQwbNlyhbXz9tZ3PjVxmrR caSF0WLH5RssFuuerGW1eLu3k92BzePsnR2MHn1bVjEGMEVx2aSk5mSWpRbp2yVwZdx//4Op 4J55RXvDcdYGxtPaXYycHBICJhIrp29jgbDFJC7cW8/WxcjFISSwlFHi3rVjLDBFB5oXsEIk pjNKfGx5DFXVzyQx6eViRpAqFgFViZNrOthAbDYBDYnvnzczg9giQPaFow+ZQBqYBf4wSvzs eAyWEBaIl/j/5DhYM6+Aq8S6lrOMEOtsJFbvXMcMEReU+DH5HtgZzAJaEpu3NbFC2PISm9e8 ZQYZKiEwmV3i6bcTzBBXCEh8m3wIqIEDKCErsekAM8RMSYmDK26wTGAUmYVk7CwkY2chGbuA kXkVo2hqQXJBcVJ6kalecWJucWleul5yfu4mRmCMnP73bOIOxvsHrA8xJgOtnMgsJZqcD4yx vJJ4Q2MzIwtTE1NjI3NLM9KElcR50x8lBQkJpCeWpGanphakFsUXleakFh9iZOLglGpgbFY1 +nnF+rhooFqBWcbCi58ivXRP2ty9zfrtk++m3y27rmZc9zK6UVjsqO95ZHm1y1q36nz/UuYt UVcjZwVrb4ji0eZNnmMSrcYdp3zkh4lP8afFj6tFTgTL1j2f9ZH1fu/TZ/W7/qtXH7x0ZdHi bQFdT10MZrQEmC7897YjpDxhvU1etNw8JZbijERDLeai4kQASJDOWacCAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrIIsWRmVeSWpSXmKPExsVy+t9jQV1dmWtBBjO2S1lcP29nceNXG6tF x5EWRosdl2+wWKx7spbV4u3eTnYHNo+zd3YwevRtWcUYwBTVwGiTkZqYklqkkJqXnJ+SmZdu q+QdHO8cb2pmYKhraGlhrqSQl5ibaqvk4hOg65aZA7RTSaEsMacUKBSQWFyspG+HaUJoiJuu BUxjhK5vSBBcj5EBGkhYw5hx//0PpoJ75hXtDcdZGxhPa3cxcnJICJhIHGhewAphi0lcuLee rYuRi0NIYDqjxMeWx1BOP5PEpJeLGUGqWARUJU6u6WADsdkENCS+f97MDGKLANkXjj5kAmlg FvjDKPGz4zFYQlggXuL/k+NgzbwCrhLrWs4yQqyzkVi9cx0zRFxQ4sfkeywgNrOAlsTmbU2s ELa8xOY1b5knMPLNQlI2C0nZLCRlCxiZVzGKphYkFxQnpeca6RUn5haX5qXrJefnbmIER+Az 6R2MqxosDjEKcDAq8fD+CL8aJMSaWFZcmXuIUYKDWUmEt0n4WpAQb0piZVVqUX58UWlOavEh xmSgtycyS4km5wOTQ15JvKGxiZmRpZG5oYWRsTlpwkrivAdbrQOFBNITS1KzU1MLUotgtjBx cEo1MKbV1FtcC5LdNfHEX74z91leuzG/6Anr7d69O7D1K8e6eOfNMYn+Mp+C2w+HLlZWMvle t0jmfwmjFMfJu5NuXH7p1BetpvzE6aOb8NV9Hsrxn0J6n3Jcdt4Qr+zocK//16qS9Tozs/ae YvB5IPtS5+sV/6LspI03em6eCgzT157Mc3Afn0BWkhJLcUaioRZzUXEiAHwwV5sEAwAA DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Cc: =?UTF-8?B?7KCV7J6s7ZuI?= , "p.wilczek@samsung.com" , =?UTF-8?B?7J2064+Z7ZmU?= , Przemyslaw Marczak Subject: [U-Boot] [PATCH v2] arm: exynos: change to use clrbits macro instead of readl/writel function X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Use setbits/clrbits macro instead of readl/writel function Signed-off-by: Inha Song Signed-off-by: Minkyu Kang Tested-by: Przemyslaw Marczak Acked-by: Jaehoon Chung --- Changes for v2: - Coding Style cleanup - add signed-off-by arch/arm/cpu/armv7/exynos/clock.c | 82 +++++++++---------------------------- 1 file changed, 20 insertions(+), 62 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 5bde9d1..6c589c9 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -870,7 +870,6 @@ static void exynos4_set_mmc_clk(int dev_index, unsigned int div) struct exynos4_clock *clk = (struct exynos4_clock *)samsung_get_base_clock(); unsigned int addr; - unsigned int val; /* * CLK_DIV_FSYS1 @@ -890,10 +889,8 @@ static void exynos4_set_mmc_clk(int dev_index, unsigned int div) dev_index -= 2; } - val = readl(addr); - val &= ~(0xff << ((dev_index << 4) + 8)); - val |= (div & 0xff) << ((dev_index << 4) + 8); - writel(val, addr); + clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8), + (div & 0xff) << ((dev_index << 4) + 8)); } /* exynos4x12: set the mmc clock */ @@ -902,7 +899,6 @@ static void exynos4x12_set_mmc_clk(int dev_index, unsigned int div) struct exynos4x12_clock *clk = (struct exynos4x12_clock *)samsung_get_base_clock(); unsigned int addr; - unsigned int val; /* * CLK_DIV_FSYS1 @@ -917,10 +913,8 @@ static void exynos4x12_set_mmc_clk(int dev_index, unsigned int div) dev_index -= 2; } - val = readl(addr); - val &= ~(0xff << ((dev_index << 4) + 8)); - val |= (div & 0xff) << ((dev_index << 4) + 8); - writel(val, addr); + clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8), + (div & 0xff) << ((dev_index << 4) + 8)); } /* exynos5: set the mmc clock */ @@ -929,7 +923,6 @@ static void exynos5_set_mmc_clk(int dev_index, unsigned int div) struct exynos5_clock *clk = (struct exynos5_clock *)samsung_get_base_clock(); unsigned int addr; - unsigned int val; /* * CLK_DIV_FSYS1 @@ -944,10 +937,8 @@ static void exynos5_set_mmc_clk(int dev_index, unsigned int div) dev_index -= 2; } - val = readl(addr); - val &= ~(0xff << ((dev_index << 4) + 8)); - val |= (div & 0xff) << ((dev_index << 4) + 8); - writel(val, addr); + clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8), + (div & 0xff) << ((dev_index << 4) + 8)); } /* exynos5: set the mmc clock */ @@ -956,7 +947,7 @@ static void exynos5420_set_mmc_clk(int dev_index, unsigned int div) struct exynos5420_clock *clk = (struct exynos5420_clock *)samsung_get_base_clock(); unsigned int addr; - unsigned int val, shift; + unsigned int shift; /* * CLK_DIV_FSYS1 @@ -967,10 +958,7 @@ static void exynos5420_set_mmc_clk(int dev_index, unsigned int div) addr = (unsigned int)&clk->div_fsys1; shift = dev_index * 10; - val = readl(addr); - val &= ~(0x3ff << shift); - val |= (div & 0x3ff) << shift; - writel(val, addr); + clrsetbits_le32(addr, 0x3ff << shift, (div & 0x3ff) << shift); } /* get_lcd_clk: return lcd clock frequency */ @@ -1061,7 +1049,6 @@ void exynos4_set_lcd_clk(void) { struct exynos4_clock *clk = (struct exynos4_clock *)samsung_get_base_clock(); - unsigned int cfg = 0; /* * CLK_GATE_BLOCK @@ -1073,9 +1060,7 @@ void exynos4_set_lcd_clk(void) * CLK_LCD1 [5] * CLK_GPS [7] */ - cfg = readl(&clk->gate_block); - cfg |= 1 << 4; - writel(cfg, &clk->gate_block); + setbits_le32(&clk->gate_block, 1 << 4); /* * CLK_SRC_LCD0 @@ -1085,10 +1070,7 @@ void exynos4_set_lcd_clk(void) * MIPI0_SEL [12:15] * set lcd0 src clock 0x6: SCLK_MPLL */ - cfg = readl(&clk->src_lcd0); - cfg &= ~(0xf); - cfg |= 0x6; - writel(cfg, &clk->src_lcd0); + clrsetbits_le32(&clk->src_lcd0, 0x9, 0x6); /* * CLK_GATE_IP_LCD0 @@ -1100,9 +1082,7 @@ void exynos4_set_lcd_clk(void) * CLK_PPMULCD0 [5] * Gating all clocks for FIMD0 */ - cfg = readl(&clk->gate_ip_lcd0); - cfg |= 1 << 0; - writel(cfg, &clk->gate_ip_lcd0); + setbits_le32(&clk->gate_ip_lcd0, 1 << 0); /* * CLK_DIV_LCD0 @@ -1114,16 +1094,13 @@ void exynos4_set_lcd_clk(void) * MIPI0_PRE_RATIO [23:20] * set fimd ratio */ - cfg &= ~(0xf); - cfg |= 0x1; - writel(cfg, &clk->div_lcd0); + clrsetbits_le32(&clk->div_lcd0, 0xe, 0x1); } void exynos5_set_lcd_clk(void) { struct exynos5_clock *clk = (struct exynos5_clock *)samsung_get_base_clock(); - unsigned int cfg = 0; /* * CLK_GATE_BLOCK @@ -1135,9 +1112,7 @@ void exynos5_set_lcd_clk(void) * CLK_LCD1 [5] * CLK_GPS [7] */ - cfg = readl(&clk->gate_block); - cfg |= 1 << 4; - writel(cfg, &clk->gate_block); + setbits_le32(&clk->gate_block, 1 << 4); /* * CLK_SRC_LCD0 @@ -1147,10 +1122,7 @@ void exynos5_set_lcd_clk(void) * MIPI0_SEL [12:15] * set lcd0 src clock 0x6: SCLK_MPLL */ - cfg = readl(&clk->src_disp1_0); - cfg &= ~(0xf); - cfg |= 0x6; - writel(cfg, &clk->src_disp1_0); + clrsetbits_le32(&clk->src_disp1_0, 0x9, 0x6); /* * CLK_GATE_IP_LCD0 @@ -1162,9 +1134,7 @@ void exynos5_set_lcd_clk(void) * CLK_PPMULCD0 [5] * Gating all clocks for FIMD0 */ - cfg = readl(&clk->gate_ip_disp1); - cfg |= 1 << 0; - writel(cfg, &clk->gate_ip_disp1); + setbits_le32(&clk->gate_ip_disp1, 1 << 0); /* * CLK_DIV_LCD0 @@ -1176,16 +1146,13 @@ void exynos5_set_lcd_clk(void) * MIPI0_PRE_RATIO [23:20] * set fimd ratio */ - cfg &= ~(0xf); - cfg |= 0x0; - writel(cfg, &clk->div_disp1_0); + clrbits_le32(&clk->div_disp1_0, 0xf); } void exynos4_set_mipi_clk(void) { struct exynos4_clock *clk = (struct exynos4_clock *)samsung_get_base_clock(); - unsigned int cfg = 0; /* * CLK_SRC_LCD0 @@ -1195,10 +1162,7 @@ void exynos4_set_mipi_clk(void) * MIPI0_SEL [12:15] * set mipi0 src clock 0x6: SCLK_MPLL */ - cfg = readl(&clk->src_lcd0); - cfg &= ~(0xf << 12); - cfg |= (0x6 << 12); - writel(cfg, &clk->src_lcd0); + clrsetbits_le32(&clk->src_lcd0, 0x9 << 12, 0x6 << 12); /* * CLK_SRC_MASK_LCD0 @@ -1208,9 +1172,7 @@ void exynos4_set_mipi_clk(void) * MIPI0_MASK [12] * set src mask mipi0 0x1: Unmask */ - cfg = readl(&clk->src_mask_lcd0); - cfg |= (0x1 << 12); - writel(cfg, &clk->src_mask_lcd0); + setbits_le32(&clk->src_mask_lcd0, 0x1 << 12); /* * CLK_GATE_IP_LCD0 @@ -1222,9 +1184,7 @@ void exynos4_set_mipi_clk(void) * CLK_PPMULCD0 [5] * Gating all clocks for MIPI0 */ - cfg = readl(&clk->gate_ip_lcd0); - cfg |= 1 << 3; - writel(cfg, &clk->gate_ip_lcd0); + setbits_le32(&clk->gate_ip_lcd0, 1 << 3); /* * CLK_DIV_LCD0 @@ -1236,9 +1196,7 @@ void exynos4_set_mipi_clk(void) * MIPI0_PRE_RATIO [23:20] * set mipi ratio */ - cfg &= ~(0xf << 16); - cfg |= (0x1 << 16); - writel(cfg, &clk->div_lcd0); + clrsetbits_le32(&clk->div_lcd0, 0xe << 16, 0x1 << 16); } /*