From patchwork Wed Feb 23 22:32:01 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anatolij Gustschin X-Patchwork-Id: 84255 X-Patchwork-Delegate: s-paulraj@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 69F67B7149 for ; Thu, 24 Feb 2011 09:32:19 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 4C43B2822D; Wed, 23 Feb 2011 23:32:16 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id r5jSUkeyo7Hc; Wed, 23 Feb 2011 23:32:16 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 8E9172822F; Wed, 23 Feb 2011 23:32:14 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A0F5F2822F for ; Wed, 23 Feb 2011 23:32:09 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id UC+nyHi5jejX for ; Wed, 23 Feb 2011 23:32:07 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-out.m-online.net (mail-out.m-online.net [212.18.0.10]) by theia.denx.de (Postfix) with ESMTP id 235872822D for ; Wed, 23 Feb 2011 23:32:04 +0100 (CET) Received: from frontend1.mail.m-online.net (frontend1.mail.intern.m-online.net [192.168.8.180]) by mail-out.m-online.net (Postfix) with ESMTP id 5F12D188B582; Wed, 23 Feb 2011 23:32:03 +0100 (CET) X-Auth-Info: 0CzLV/rVfjJ+Yofk5QlxJucAqTAiyz+J/E5H//GNRRc= Received: from wker (p4FDE6EBF.dip.t-dialin.net [79.222.110.191]) (using TLSv1 with cipher DHE-RSA-AES128-SHA (128/128 bits)) (No client certificate requested) by mail.mnet-online.de (Postfix) with ESMTPSA id 6CB421C00159; Wed, 23 Feb 2011 23:32:03 +0100 (CET) Date: Wed, 23 Feb 2011 23:32:01 +0100 From: Anatolij Gustschin To: jacopo mondi Message-ID: <20110223233201.09aee7e4@wker> In-Reply-To: <20110222173430.06aa118b@BlackBox> References: <20110216172917.4a5e83cc@BlackBox> <4D5C09EB.4090408@emk-elektronik.de> <20110222173430.06aa118b@BlackBox> X-Mailer: Claws Mail 3.7.6 (GTK+ 2.22.0; x86_64-pc-linux-gnu) Mime-Version: 1.0 Cc: u-boot@lists.denx.de Subject: Re: [U-Boot] building enc28j60 for omap3: SILICON ERRATA X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Hi, On Tue, 22 Feb 2011 17:34:30 +0100 jacopo mondi wrote: ... > Second issue is related to enc identification. > The following code section: > > phid1 = phy_read(enc, PHY_REG_PHID1); > phid2 = phy_read(enc, PHY_REG_PHID2) & ENC_PHID2_MASK; > if (phid1 != ENC_PHID1_VALUE || phid2 != ENC_PHID2_VALUE) { > printf("%s: failed to identify PHY. Found > %04x:%04x\n", enc->dev->name, > phid1, phid2); > return -1; > } > > fails because phy_read instructions return 0 or random values (0xB0B0 > or 0xB000). > Linux driver does not perform such tests, so I've tried removing them. No, please do not remove them. Fix the register access problem instead. > Anyway all read and write to enc fails. > Could that be related to omap3_spi implementation? Yes. If you use the omap3_spi driver in current mainline tree, then definitely the omap3_spi driver is the problem. enc28j60 register and buffer access can not work with this current driver version. We experienced problems with enc28j60 register access on a iMX31 based board as there were among other things some byte order issues in the spi driver. When using spi clock above 2 MHz we also have seen seemingly random data when reading the enc registers. Be aware that there are two kinds of spi transfers for enc register access: two bytes long transfers and three bytes long transfers with a dummy byte. The spi chip select signal have to be active as long as these tx/rx transfers didn't completed and may not be deactivated in between. Also the spi transfer is full-duplex for enc28j60 register and buffers access. With a properly working spi driver the enc28j60 driver in U-Boot works well. > I can confirm that same same board I'm using for test works great > under Linux, so it is not an hardware issue. This is the omap3_spi driver issue. You can apply the attached patch for enc28j60 driver to be able to start single register accesses on the U-Boot command line. Then you can start fixing the spi driver code. Implement fixes in the spi driver and test the register access using the enc commands added by the path. You will have to implement the Master Transmit-Receive Mode (full-duplex) in the omap3_spi driver for proper enc28j60 register and buffer access. Currently this driver is using Tx-Only Mode for transmitting a Rx-Only Mode for receiving. But it shouldn't be too hard to fix the spi driver. What is needed is a kind of merge of omap3_spi_read/omap3_spi_write routines. HTH Anatolij diff --git a/drivers/net/enc28j60.c b/drivers/net/enc28j60.c index 5731bdb..784d1dd 100644 --- a/drivers/net/enc28j60.c +++ b/drivers/net/enc28j60.c @@ -21,6 +21,7 @@ */ #include +#include #include #include #include @@ -926,6 +927,7 @@ static void enc_halt(struct eth_device *dev) enc_release_bus(enc); } +enc_dev_t *genc; /* * This is the only exported function. * @@ -974,5 +976,65 @@ int enc28j60_initialize(unsigned int bus, unsigned int cs, #if defined(CONFIG_CMD_MII) miiphy_register(dev->name, enc_miiphy_read, enc_miiphy_write); #endif + genc = enc; return 0; } + + +int do_enc(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + char *cmd; + u32 reg; + u32 val; + + /* at least two arguments */ + if (argc < 3) + return cmd_usage(cmdtp); + + cmd = argv[1]; + if (strcmp(cmd, "r") == 0) { + if (argc < 3) + return cmd_usage(cmdtp); + + reg = simple_strtoul(argv[2], NULL, 16); + printf("reg. 0x%02lx: 0x%02lx\n", (ulong)reg, (ulong)enc_r8(genc, (u16)reg)); + return 0; + } + if (strcmp(cmd, "pr") == 0) { + if (argc < 3) + return cmd_usage(cmdtp); + + reg = simple_strtoul(argv[2], NULL, 16); + printf("phy reg. 0x%02lx: 0x%04lx\n", (ulong)reg, (ulong)phy_read(genc, (u8)reg)); + return 0; + } + if (strcmp(cmd, "w") == 0) { + if (argc < 4) + return cmd_usage(cmdtp); + + reg = simple_strtoul(argv[2], NULL, 16); + val = simple_strtoul(argv[3], NULL, 16); + enc_w8(genc, (u16)reg, (u8)val); + return 0; + } + if (strcmp(cmd, "pw") == 0) { + if (argc < 4) + return cmd_usage(cmdtp); + + reg = simple_strtoul(argv[2], NULL, 16); + val = simple_strtoul(argv[3], NULL, 16); + phy_write(genc, (u8)reg, (u16)val); + return 0; + } + /* No subcommand */ + return 1; +} + +U_BOOT_CMD( + enc, 4, 1, do_enc, + "enc28j60 register read/write", + "r - read register\n" + "enc w - write register\n" + "enc pr - read PHY register\n" + "enc pw - write PHY register" +);