From patchwork Fri Jul 20 14:24:38 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Beno=C3=AEt_Th=C3=A9baudeau?= X-Patchwork-Id: 172282 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id ED4F02C03AC for ; Sat, 21 Jul 2012 00:19:58 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 3901A2807F; Fri, 20 Jul 2012 16:19:55 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Ag8mZ5M9CL8e; Fri, 20 Jul 2012 16:19:54 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 494DE28080; Fri, 20 Jul 2012 16:19:53 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 330BD28080 for ; Fri, 20 Jul 2012 16:19:50 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id RFcvr2VhDTeh for ; Fri, 20 Jul 2012 16:19:46 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from zose-mta15.web4all.fr (zose-mta15.web4all.fr [176.31.217.11]) by theia.denx.de (Postfix) with ESMTP id EC30E2807F for ; Fri, 20 Jul 2012 16:19:43 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by zose-mta15.web4all.fr (Postfix) with ESMTP id DB08132143; Fri, 20 Jul 2012 16:22:10 +0200 (CEST) X-Virus-Scanned: amavisd-new at zose1.web4all.fr Received: from zose-mta15.web4all.fr ([127.0.0.1]) by localhost (zose-mta15.web4all.fr [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 9up1jm88jqzI; Fri, 20 Jul 2012 16:22:10 +0200 (CEST) Received: from zose-store12.web4all.fr (zose-store-12.w4a.fr [178.33.204.48]) by zose-mta15.web4all.fr (Postfix) with ESMTP id 3C2F932141; Fri, 20 Jul 2012 16:22:10 +0200 (CEST) Date: Fri, 20 Jul 2012 16:24:38 +0200 (CEST) From: =?utf-8?Q?Beno=C3=AEt_Th=C3=A9baudeau?= To: u-boot@lists.denx.de Message-ID: <194408868.336913.1342794278862.JavaMail.root@advansee.com> In-Reply-To: <1227195557.336910.1342794274777.JavaMail.root@advansee.com> MIME-Version: 1.0 X-Originating-IP: [88.188.188.98] X-Mailer: Zimbra 7.2.0_GA_2669 (ZimbraWebClient - FF3.0 (Win)/7.2.0_GA_2669) Subject: [U-Boot] [PATCH] rtc: imxdi: Initial support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Add support for Freescale's i.MX DryIce RTC, present on i.MX25. Signed-off-by: Benoît Thébaudeau Cc: Wolfgang Denk Cc: Stefano Babic --- .../drivers/rtc/Makefile | 1 + /dev/null => u-boot-66714b1/drivers/rtc/imxdi.c | 224 ++++++++++++++++++++ 2 files changed, 225 insertions(+) create mode 100644 u-boot-66714b1/drivers/rtc/imxdi.c diff --git u-boot-66714b1.orig/drivers/rtc/Makefile u-boot-66714b1/drivers/rtc/Makefile index faf4fcd..aeeea37 100644 --- u-boot-66714b1.orig/drivers/rtc/Makefile +++ u-boot-66714b1/drivers/rtc/Makefile @@ -43,6 +43,7 @@ COBJS-$(CONFIG_RTC_DS164x) += ds164x.o COBJS-$(CONFIG_RTC_DS174x) += ds174x.o COBJS-$(CONFIG_RTC_DS3231) += ds3231.o COBJS-$(CONFIG_RTC_FTRTC010) += ftrtc010.o +COBJS-$(CONFIG_RTC_IMXDI) += imxdi.o COBJS-$(CONFIG_RTC_ISL1208) += isl1208.o COBJS-$(CONFIG_RTC_M41T11) += m41t11.o COBJS-$(CONFIG_RTC_M41T60) += m41t60.o diff --git u-boot-66714b1/drivers/rtc/imxdi.c u-boot-66714b1/drivers/rtc/imxdi.c new file mode 100644 index 0000000..c2be842 --- /dev/null +++ u-boot-66714b1/drivers/rtc/imxdi.c @@ -0,0 +1,224 @@ +/* + * (C) Copyright 2009-2012 ADVANSEE + * Benoît Thébaudeau + * + * Based on the Linux rtc-imxdi.c driver, which is: + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2010 Orex Computed Radiography + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Date & Time support for Freescale i.MX DryIce RTC + */ + +#include +#include +#include + +#if defined(CONFIG_CMD_DATE) + +#include +#include + +/* DryIce Register Definitions */ + +#define DTCMR 0x00 /* Time Counter MSB Reg */ +#define DTCLR 0x04 /* Time Counter LSB Reg */ + +#define DCAMR 0x08 /* Clock Alarm MSB Reg */ +#define DCALR 0x0c /* Clock Alarm LSB Reg */ +#define DCAMR_UNSET 0xFFFFFFFF /* doomsday - 1 sec */ + +#define DCR 0x10 /* Control Reg */ +#define DCR_TCE (1 << 3) /* Time Counter Enable */ + +#define DSR 0x14 /* Status Reg */ +#define DSR_WBF (1 << 10) /* Write Busy Flag */ +#define DSR_WNF (1 << 9) /* Write Next Flag */ +#define DSR_WCF (1 << 8) /* Write Complete Flag */ +#define DSR_WEF (1 << 7) /* Write Error Flag */ +#define DSR_CAF (1 << 4) /* Clock Alarm Flag */ +#define DSR_NVF (1 << 1) /* Non-Valid Flag */ +#define DSR_SVF (1 << 0) /* Security Violation Flag */ + +#define DIER 0x18 /* Interrupt Enable Reg */ +#define DIER_WNIE (1 << 9) /* Write Next Interrupt Enable */ +#define DIER_WCIE (1 << 8) /* Write Complete Interrupt Enable */ +#define DIER_WEIE (1 << 7) /* Write Error Interrupt Enable */ +#define DIER_CAIE (1 << 4) /* Clock Alarm Interrupt Enable */ + +/* + * This function attempts to clear the dryice write-error flag. + * + * A dryice write error is similar to a bus fault and should not occur in + * normal operation. Clearing the flag requires another write, so the root + * cause of the problem may need to be fixed before the flag can be cleared. + */ +static void clear_write_error(void) +{ + int cnt; + + puts("### Warning: RTC - Register write error!\n"); + + /* clear the write error flag */ + __raw_writel(DSR_WEF, IMX_DRYICE_BASE + DSR); + + /* wait for it to take effect */ + for (cnt = 0; cnt < 1000; cnt++) { + if ((__raw_readl(IMX_DRYICE_BASE + DSR) & DSR_WEF) == 0) + return; + udelay(10); + } + puts("### Error: RTC - Cannot clear write-error flag!\n"); +} + +/* + * Write a dryice register and wait until it completes. + * + * This function uses interrupt flags to determine when the + * write has completed. + */ +static int di_write_wait(u32 val, int reg) +{ + int cnt; + int ret = 0; + int rc = 0; + + /* do the register write */ + __raw_writel(val, IMX_DRYICE_BASE + reg); + + /* wait for the write to finish */ + for (cnt = 0; cnt < 100; cnt++) { + if ((__raw_readl(IMX_DRYICE_BASE + DSR) & + (DSR_WCF | DSR_WEF)) != 0) { + ret = 1; + break; + } + udelay(10); + } + if (ret == 0) + printf("### Warning: RTC - Write-wait timeout " + "val = 0x%.8x reg = 0x%.8x\n", val, reg); + + /* check for write error */ + if (__raw_readl(IMX_DRYICE_BASE + DSR) & DSR_WEF) { + clear_write_error(); + rc = -1; + } + + return rc; +} + +/* + * Initialize dryice hardware + */ +static int di_init(void) +{ + int rc = 0; + + /* mask all interrupts */ + __raw_writel(0, IMX_DRYICE_BASE + DIER); + + /* put dryice into valid state */ + if (__raw_readl(IMX_DRYICE_BASE + DSR) & DSR_NVF) { + rc = di_write_wait(DSR_NVF | DSR_SVF, DSR); + if (rc) + goto err; + } + + /* initialize alarm */ + rc = di_write_wait(DCAMR_UNSET, DCAMR); + if (rc) + goto err; + rc = di_write_wait(0, DCALR); + if (rc) + goto err; + + /* clear alarm flag */ + if (__raw_readl(IMX_DRYICE_BASE + DSR) & DSR_CAF) { + rc = di_write_wait(DSR_CAF, DSR); + if (rc) + goto err; + } + + /* the timer won't count if it has never been written to */ + if (__raw_readl(IMX_DRYICE_BASE + DTCMR) == 0) { + rc = di_write_wait(0, DTCMR); + if (rc) + goto err; + } + + /* start keeping time */ + if (!(__raw_readl(IMX_DRYICE_BASE + DCR) & DCR_TCE)) { + rc = di_write_wait(__raw_readl(IMX_DRYICE_BASE + DCR) | DCR_TCE, + DCR); + if (rc) + goto err; + } + + return 0; + +err: + return rc; +} + +int rtc_get(struct rtc_time *tmp) +{ + unsigned long now; + int rc; + + rc = di_init(); + if (rc) + goto err; + + now = __raw_readl(IMX_DRYICE_BASE + DTCMR); + to_tm(now, tmp); + +err: + return rc; +} + +int rtc_set(struct rtc_time *tmp) +{ + unsigned long now; + int rc; + + rc = di_init(); + if (rc) + goto err; + + now = mktime(tmp->tm_year, tmp->tm_mon, tmp->tm_mday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); + /* zero the fractional part first */ + rc = di_write_wait(0, DTCLR); + if (rc == 0) + rc = di_write_wait(now, DTCMR); + +err: + return rc; +} + +void rtc_reset(void) +{ + di_init(); +} + +#endif