From patchwork Wed Mar 5 16:57:45 2014
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: 7bit
X-Patchwork-Submitter: Przemyslaw Marczak
X-Patchwork-Id: 327083
X-Patchwork-Delegate: trini@ti.com
Return-Path:
X-Original-To: incoming@patchwork.ozlabs.org
Delivered-To: patchwork-incoming@bilbo.ozlabs.org
Received: from theia.denx.de (theia.denx.de [85.214.87.163])
by ozlabs.org (Postfix) with ESMTP id 809FE2C00BD
for ;
Thu, 6 Mar 2014 03:58:09 +1100 (EST)
Received: from localhost (localhost [127.0.0.1])
by theia.denx.de (Postfix) with ESMTP id 871D44B5E9;
Wed, 5 Mar 2014 17:58:07 +0100 (CET)
X-Virus-Scanned: Debian amavisd-new at theia.denx.de
Received: from theia.denx.de ([127.0.0.1])
by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024)
with ESMTP id dXm-h82Vwv+M; Wed, 5 Mar 2014 17:58:07 +0100 (CET)
Received: from theia.denx.de (localhost [127.0.0.1])
by theia.denx.de (Postfix) with ESMTP id 80FD04B5F1;
Wed, 5 Mar 2014 17:58:05 +0100 (CET)
Received: from localhost (localhost [127.0.0.1])
by theia.denx.de (Postfix) with ESMTP id 8EE704B5FA
for ; Wed, 5 Mar 2014 17:58:03 +0100 (CET)
X-Virus-Scanned: Debian amavisd-new at theia.denx.de
Received: from theia.denx.de ([127.0.0.1])
by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024)
with ESMTP id AfuDSWZw54Us for ;
Wed, 5 Mar 2014 17:58:00 +0100 (CET)
X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5
NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested)
Received: from mailout1.w1.samsung.com (mailout1.w1.samsung.com
[210.118.77.11]) by theia.denx.de (Postfix) with ESMTPS id 6A0574B5E9
for ; Wed, 5 Mar 2014 17:57:56 +0100 (CET)
Received: from eucpsbgm1.samsung.com (unknown [203.254.199.244])
by mailout1.w1.samsung.com
(Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit
(built Nov
17 2011)) with ESMTP id <0N1Z00D1D34J5D00@mailout1.w1.samsung.com>
for u-boot@lists.denx.de; Wed, 05 Mar 2014 16:57:55 +0000 (GMT)
X-AuditID: cbfec7f4-b7f796d000005a13-b7-531757933440
Received: from eusync3.samsung.com ( [203.254.199.213])
by eucpsbgm1.samsung.com (EUCPMTA) with SMTP id F5.9B.23059.39757135;
Wed, 05 Mar 2014 16:57:55 +0000 (GMT)
Received: from AMDC1186.digital.local ([106.116.147.185])
by eusync3.samsung.com
(Oracle Communications Messaging Server 7u4-23.01(7.0.4.23.0) 64bit
(built Aug
10 2011)) with ESMTPA id <0N1Z00GR934GPJ20@eusync3.samsung.com>; Wed,
05 Mar 2014 16:57:55 +0000 (GMT)
From: Przemyslaw Marczak
To: u-boot@lists.denx.de
Date: Wed, 05 Mar 2014 17:57:45 +0100
Message-id:
<1882e4320da26486d3759d81f1b440a0f89457b8.1394038415.git.p.marczak@samsung.com>
X-Mailer: git-send-email 1.7.9.5
In-reply-to:
References:
X-Brightmail-Tracker:
H4sIAAAAAAAAA+NgFnrOJMWRmVeSWpSXmKPExsVy+t/xq7qTw8WDDZpn8Vic+vOY0eLVv0vs
Fh1HWhgtdly+wWIxefF8Zou3ezvZHdg8zt7ZwejRt2UVo8fxG9uZApijuGxSUnMyy1KL9O0S
uDKO/nzIVnBArqLp3xnWBsadkl2MnBwSAiYS13afZIewxSQu3FvP1sXIxSEksJRR4siN2ywQ
Th+TxNpNLxhBqtgEDCT2XDrDDGKLCEhI/Oq/ChZnFtjNKDFxhjmILSwQJ9F6aT4biM0ioCpx
Z3ojE4jNKxAr8aT3JFA9B9A2BYk5k2xAwpxA5WsXnGYBsYWASp523mKcwMi7gJFhFaNoamly
QXFSeq6hXnFibnFpXrpecn7uJkZI4HzZwbj4mNUhRgEORiUe3g1+4sFCrIllxZW5hxglOJiV
RHjb3IBCvCmJlVWpRfnxRaU5qcWHGJk4OKUaGNUnvr/W+tF0+9ynbGf0n75Jk6m/PsHKjJ3z
5Vo3Ti7JE/ufez4u7Emexvtv34yOzhsbo0VdHzqtXFBpM7dfzZSJK+af2+yHrV8LUvS/TL2S
ecKo7ZOwQskljYY9yU6XXGIPnr+7L8VjRZeEZbmg957q0zNvla8MC7skc4Sprin4Zov0czt3
BiWW4oxEQy3mouJEAHDIqQL6AQAA
Cc: Akshay Saraswat , Tom Rini ,
ARUN MANKUZHI ,
Przemyslaw Marczak
Subject: [U-Boot] [PATCH V2 1/3] cpu: exynos4: ace_sha: add hardware random
number generator support.
X-BeenThere: u-boot@lists.denx.de
X-Mailman-Version: 2.1.11
Precedence: list
List-Id: U-Boot discussion
List-Unsubscribe: ,
List-Archive:
List-Post:
List-Help:
List-Subscribe: ,
MIME-Version: 1.0
Sender: u-boot-bounces@lists.denx.de
Errors-To: u-boot-bounces@lists.denx.de
This patch adds implementation of function hw_rand() based on exynos
security sub system.
Signed-off-by: Przemyslaw Marczak
cc: Akshay Saraswat
cc: ARUN MANKUZHI
cc: Minkyu Kang
---
Changes v2:
- none
arch/arm/include/asm/arch-exynos/cpu.h | 4 ++--
drivers/crypto/ace_sha.c | 41 ++++++++++++++++++++++++++++++++
drivers/crypto/ace_sha.h | 8 ++++---
3 files changed, 48 insertions(+), 5 deletions(-)
diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h
index bccce63..a5c280d 100644
--- a/arch/arm/include/asm/arch-exynos/cpu.h
+++ b/arch/arm/include/asm/arch-exynos/cpu.h
@@ -48,7 +48,7 @@
#define EXYNOS4_GPIO_PART4_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4_DP_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4_SPI_ISP_BASE DEVICE_NOT_AVAILABLE
-#define EXYNOS4_ACE_SFR_BASE DEVICE_NOT_AVAILABLE
+#define EXYNOS4_ACE_SFR_BASE 0x10830000
#define EXYNOS4_DMC_PHY_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4_AUDIOSS_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4_USB_HOST_XHCI_BASE DEVICE_NOT_AVAILABLE
@@ -87,7 +87,7 @@
#define EXYNOS4X12_I2S_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4X12_SPI_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4X12_SPI_ISP_BASE DEVICE_NOT_AVAILABLE
-#define EXYNOS4X12_ACE_SFR_BASE DEVICE_NOT_AVAILABLE
+#define EXYNOS4X12_ACE_SFR_BASE 0x10830000
#define EXYNOS4X12_DMC_PHY_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4X12_AUDIOSS_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4X12_USB_HOST_XHCI_BASE DEVICE_NOT_AVAILABLE
diff --git a/drivers/crypto/ace_sha.c b/drivers/crypto/ace_sha.c
index acbafde..d12a507 100644
--- a/drivers/crypto/ace_sha.c
+++ b/drivers/crypto/ace_sha.c
@@ -111,3 +111,44 @@ void hw_sha1(const unsigned char *pbuf, unsigned int buf_len,
if (ace_sha_hash_digest(pbuf, buf_len, pout, ACE_SHA_TYPE_SHA1))
debug("ACE was not setup properly or it is faulty\n");
}
+
+unsigned int hw_rand(void)
+{
+ struct exynos_ace_sfr *reg =
+ (struct exynos_ace_sfr *)samsung_get_base_ace_sfr();
+ int status, i;
+ int seed[5];
+ unsigned int ret = 0;
+
+ /* Seed data */
+ for (i = 0; i < ACE_HASH_PRNG_REG_NUM; i++)
+ writel(seed[i], ®->hash_seed[i]);
+
+ status = 0;
+ /* Wait for seed setup done */
+ while (!(status & ACE_HASH_SEEDSETTING_MASK)) {
+ status = readl(®->hash_status);
+ if (status & ACE_HASH_PRNGERROR_MASK)
+ return 0;
+ }
+
+ /* Start PRNG */
+ writel(ACE_HASH_ENGSEL_PRNG | ACE_HASH_STARTBIT_ON, ®->hash_control);
+
+ status = 0;
+ /* Wait for PRNG done */
+ while (!(status & ACE_HASH_PRNGDONE_MASK)) {
+ status = readl(®->hash_status);
+ if (status & ACE_HASH_PRNGERROR_MASK)
+ return 0;
+ }
+
+ /* Clear Done IRQ */
+ writel(ACE_HASH_PRNGDONE_MASK, ®->hash_status);
+
+ /* Read a PRNG result */
+ for (i = 0; i < ACE_HASH_PRNG_REG_NUM; i++)
+ ret += readl(®->hash_prng[i]);
+
+ return ret;
+}
diff --git a/drivers/crypto/ace_sha.h b/drivers/crypto/ace_sha.h
index a426d52..f1097f7 100644
--- a/drivers/crypto/ace_sha.h
+++ b/drivers/crypto/ace_sha.h
@@ -72,9 +72,10 @@ struct exynos_ace_sfr {
unsigned char res12[0x30];
unsigned int hash_result[8];
unsigned char res13[0x20];
- unsigned int hash_seed[8];
- unsigned int hash_prng[8];
- unsigned char res14[0x180];
+ unsigned int hash_seed[5];
+ unsigned char res14[12];
+ unsigned int hash_prng[5];
+ unsigned char res15[0x18c];
unsigned int pka_sfr[5]; /* base + 0x700 */
};
@@ -291,6 +292,7 @@ struct exynos_ace_sfr {
#define ACE_HASH_PRNGERROR_MASK (1 << 7)
#define ACE_HASH_PRNGERROR_OFF (0 << 7)
#define ACE_HASH_PRNGERROR_ON (1 << 7)
+#define ACE_HASH_PRNG_REG_NUM 5
#define ACE_SHA_TYPE_SHA1 1
#define ACE_SHA_TYPE_SHA256 2