From patchwork Fri Feb 11 11:16:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bough Chen X-Patchwork-Id: 1591602 X-Patchwork-Delegate: jh80.chung@samsung.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4JwBjC6BnPz9s0r for ; Fri, 11 Feb 2022 22:49:03 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 5638283A37; Fri, 11 Feb 2022 12:48:52 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=nxp.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 02AFE83A10; Fri, 11 Feb 2022 12:48:51 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2 Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 4C33183A4C for ; Fri, 11 Feb 2022 12:48:46 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=haibo.chen@nxp.com Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 169531A1B6B; Fri, 11 Feb 2022 12:48:46 +0100 (CET) Received: from aprdc01srsp001v.ap-rdc01.nxp.com (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id D32071A1B62; Fri, 11 Feb 2022 12:48:45 +0100 (CET) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id 50107183AC94; Fri, 11 Feb 2022 19:48:44 +0800 (+08) From: haibo.chen@nxp.com To: peng.fan@nxp.com, jh80.chung@samsung.com, festevam@gmail.com, sean.anderson@seco.com, u-boot@lists.denx.de, marex@denx.de, aford173@gmail.com, tharvey@gateworks.com, andrey.zhizhikin@leica-geosystems.com Cc: uboot-imx@nxp.com, haibo.chen@nxp.com Subject: [PATCH 3/3] mmc: fsl_esdhc_imx: correct the actual card clock Date: Fri, 11 Feb 2022 19:16:57 +0800 Message-Id: <1644578217-8947-3-git-send-email-haibo.chen@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1644578217-8947-1-git-send-email-haibo.chen@nxp.com> References: <1644578217-8947-1-git-send-email-haibo.chen@nxp.com> X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean From: Haibo Chen The original code logic can not show the correct card clock, and also has one risk when the div is 0. Because there is div -=1 before. So move the operation before div -=1, and also involve ddr_pre_div to get the correct value. Signed-off-by: Haibo Chen Reviewed-by: Marek Vasut --- drivers/mmc/fsl_esdhc_imx.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c index 0be7cae1e5..0ea7b0b50c 100644 --- a/drivers/mmc/fsl_esdhc_imx.c +++ b/drivers/mmc/fsl_esdhc_imx.c @@ -609,6 +609,8 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock) while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16) div++; + mmc->clock = sdhc_clk / pre_div / div / ddr_pre_div; + pre_div >>= 1; div -= 1; @@ -630,7 +632,6 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock) else esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN); - mmc->clock = sdhc_clk / pre_div / div; priv->clock = clock; }