| Message ID | 161861634943.298230.1297757186016100500.stgit@localhost |
|---|---|
| State | Superseded |
| Delegated to: | Tom Rini |
| Headers | show |
| Series | arm64: synquacer: Add SynQuacer/DeveloperBox support | expand |
Hi, I found that I need to enable CONFIG_CMD_FS_GENERIC for enabling distroboot support. I'll fix it in the next version. Thank you, 2021年4月17日(土) 8:39 Masami Hiramatsu <masami.hiramatsu@linaro.org>: > > Add the DeveloperBox 96boards EE support. This board is also > known as Socionext SynQuacer E-Series. It contians one "SC2A11" > SoC, which has 24-cores of arm Cortex-A53, and 4 DDR3 slots, > 3 PCIe slots (1 4x port and 2 1x ports which are expanded via > PCIe bridge chip), 2 USB 3.0 ports and 2 USB 2.0 ports, 2 SATA > ports and 1 GbE, 64MB NOR flash and 8GB eMMC on standard > MicroATX Form Factor. > > For more information, see this page; > https://www.96boards.org/product/developerbox/ > > Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org> > --- > Changes in v2: > - Do not include arch/gpio.h and remove arch-sc2a11/gpio.h. > - Remove non-UEFI boot commands. > - Use Distro boot. > - Remove NOR-connected SPI node by path instead of alias. > - Rename configs/SynQuacer_defconfig to > configs/synquacer_developerbox_defconfig. > - Rename include/configs/SynQuacer.h to include/configs/synquacer.h. > - Move README under doc/board/socionext/ and make it .rst text. > --- > arch/arm/Kconfig | 15 +++ > board/socionext/developerbox/Kconfig | 36 +++++++ > board/socionext/developerbox/MAINTAINERS | 13 ++ > board/socionext/developerbox/Makefile | 9 ++ > board/socionext/developerbox/developerbox.c | 145 +++++++++++++++++++++++++++ > configs/synquacer_developerbox_defconfig | 93 +++++++++++++++++ > doc/board/index.rst | 1 > doc/board/socionext/developerbox.rst | 87 ++++++++++++++++ > doc/board/socionext/index.rst | 9 ++ > include/configs/synquacer.h | 106 ++++++++++++++++++++ > 10 files changed, 514 insertions(+) > create mode 100644 board/socionext/developerbox/Kconfig > create mode 100644 board/socionext/developerbox/MAINTAINERS > create mode 100644 board/socionext/developerbox/Makefile > create mode 100644 board/socionext/developerbox/developerbox.c > create mode 100644 configs/synquacer_developerbox_defconfig > create mode 100644 doc/board/socionext/developerbox.rst > create mode 100644 doc/board/socionext/index.rst > create mode 100644 include/configs/synquacer.h > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > index fba28323cd..1caea3ac58 100644 > --- a/arch/arm/Kconfig > +++ b/arch/arm/Kconfig > @@ -1675,6 +1675,20 @@ config ARCH_UNIPHIER > Support for UniPhier SoC family developed by Socionext Inc. > (formerly, System LSI Business Division of Panasonic Corporation) > > +config ARCH_SYNQUACER > + bool "Socionext SynQuacer SoCs" > + select ARM64 > + select ONLY_GENERIC_GPIO > + select DM > + select GIC_V3 > + select PSCI_RESET > + select SYSRESET > + select SYSRESET_PSCI > + select OF_CONTROL > + help > + Support for SynQuacer SoC family developed by Socionext Inc. > + This SoC is used on 96boards EE DeveloperBox. > + > config ARCH_STM32 > bool "Support STMicroelectronics STM32 MCU with cortex M" > select CPU_V7M > @@ -2022,6 +2036,7 @@ source "board/hisilicon/poplar/Kconfig" > source "board/isee/igep003x/Kconfig" > source "board/kontron/sl28/Kconfig" > source "board/myir/mys_6ulx/Kconfig" > +source "board/socionext/developerbox/Kconfig" > source "board/spear/spear300/Kconfig" > source "board/spear/spear310/Kconfig" > source "board/spear/spear320/Kconfig" > diff --git a/board/socionext/developerbox/Kconfig b/board/socionext/developerbox/Kconfig > new file mode 100644 > index 0000000000..706b8dc0f1 > --- /dev/null > +++ b/board/socionext/developerbox/Kconfig > @@ -0,0 +1,36 @@ > +if ARCH_SYNQUACER > + > +choice > + prompt "SC2A11 Cortex-A53 MPCore 24cores" > + optional > + > +config TARGET_DEVELOPERBOX > + bool "Socionext DeveloperBox" > + select PCI > + select DM_PCI > + select PCIE_ECAM_SYNQUACER > + select SYS_DISABLE_DCACHE_OPS > + select OF_BOARD_SETUP > + help > + Choose this option if you build the U-Boot for the DeveloperBox > + 96boards Enterprise Edition. > + This board will booted from SCP firmware and it enables SMMU, thus > + the dcache is updated automatically when DMA operation is executed. > +endchoice > + > +config SYS_SOC > + default "sc2a11" > + > +if TARGET_DEVELOPERBOX > + > +config SYS_BOARD > + default "developerbox" > + > +config SYS_VENDOR > + default "socionext" > + > +config SYS_CONFIG_NAME > + default "synquacer" > + > +endif > +endif > diff --git a/board/socionext/developerbox/MAINTAINERS b/board/socionext/developerbox/MAINTAINERS > new file mode 100644 > index 0000000000..d10ad3b8f7 > --- /dev/null > +++ b/board/socionext/developerbox/MAINTAINERS > @@ -0,0 +1,13 @@ > +DEVELOPER BOX > +M: Masami Hiramatsu <masami.hiramatsu@linaro.org> > +M: Jassi Brar <jaswinder.singh@linaro.org> > +S: Maintained > +F: arch/arm/dts/synquacer-* > +F: board/socionext/developerbox/* > +F: configs/synquacer_developerbox_defconfig > +F: drivers/mmc/f_sdh30.c > +F: drivers/net/sni_netsec.c > +F: drivers/pci/pcie_ecam_synquacer.c > +F: drivers/spi/spi-synquacer.c > +F: include/configs/synquacer.h > +F: doc/board/socionext/developerbox.rst > diff --git a/board/socionext/developerbox/Makefile b/board/socionext/developerbox/Makefile > new file mode 100644 > index 0000000000..4a46de995a > --- /dev/null > +++ b/board/socionext/developerbox/Makefile > @@ -0,0 +1,9 @@ > +# > +# Author: Masami Hiramatsu <masami.hiramatsu@linaro.org> > +# > +# Copyright (C) 2021 Linaro Ltd. > +# > +# SPDX-License-Identifier: GPL-2.0+ > +# > + > +obj-y := developerbox.o > diff --git a/board/socionext/developerbox/developerbox.c b/board/socionext/developerbox/developerbox.c > new file mode 100644 > index 0000000000..3e943a279c > --- /dev/null > +++ b/board/socionext/developerbox/developerbox.c > @@ -0,0 +1,145 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * u-boot/board/socionext/developerbox/developerbox.c > + * > + * Copyright (C) 2016-2017 Socionext Inc. > + * Copyright (C) 2021 Linaro Ltd. > + */ > +#include <asm/types.h> > +#include <asm/armv8/mmu.h> > +#include <asm/global_data.h> > +#include <asm/io.h> > +#include <common.h> > +#include <env_internal.h> > +#include <fdt_support.h> > +#include <log.h> > + > +static struct mm_region sc2a11_mem_map[] = { > + { > + .virt = 0x0UL, > + .phys = 0x0UL, > + .size = 0x80000000UL, > + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | > + PTE_BLOCK_OUTER_SHARE > + }, { > + /* 1st DDR block */ > + .virt = 0x80000000UL, > + .phys = 0x80000000UL, > + .size = PHYS_SDRAM_SIZE, > + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | > + PTE_BLOCK_OUTER_SHARE > + }, { > + /* 2nd DDR place holder */ > + 0, > + }, { > + /* 3rd DDR place holder */ > + 0, > + }, { > + /* List terminator */ > + 0, > + } > +}; > + > +struct mm_region *mem_map = sc2a11_mem_map; > + > +#define DDR_REGION_INDEX(i) (1 + (i)) > +#define MAX_DDR_REGIONS 3 > + > +struct draminfo_entry { > + u64 base; > + u64 size; > +}; > + > +struct draminfo { > + u32 nr_regions; > + u32 reserved; > + struct draminfo_entry entry[3]; > +}; > + > +struct draminfo *synquacer_draminfo = (void *)SQ_DRAMINFO_BASE; > + > +DECLARE_GLOBAL_DATA_PTR; > + > +#define LOAD_OFFSET 0x100 > + > +/* > + * Miscellaneous platform dependent initialisations > + */ > +int board_init(void) > +{ > + gd->bd->bi_boot_params = CONFIG_SYS_LOAD_ADDR + LOAD_OFFSET; > + > + gd->env_addr = (ulong)&default_environment[0]; > + > + return 0; > +} > + > +int ft_board_setup(void *blob, struct bd_info *bd) > +{ > + /* Remove SPI NOR for making System DT compatible with EDK2 */ > + fdt_del_node_and_alias(blob, "spi_nor"); > + > + return 0; > +} > + > +/* > + * DRAM configuration > + */ > + > +int dram_init(void) > +{ > + struct draminfo_entry *ent = synquacer_draminfo->entry; > + struct mm_region *mr; > + int i, ri; > + > + if (synquacer_draminfo->nr_regions < 1) { > + log_err("Failed to get correct DRAM information\n"); > + return -1; > + } > + > + /* > + * U-Boot RAM size must be under the first DRAM region so that it doesn't > + * access secure memory which is at the end of the first DRAM region. > + */ > + gd->ram_size = ent[0].size; > + > + /* Update memory region maps */ > + for (i = 0; i < synquacer_draminfo->nr_regions; i++) { > + if (i >= MAX_DDR_REGIONS) > + break; > + > + ri = DDR_REGION_INDEX(i); > + mem_map[ri].phys = ent[i].base; > + mem_map[ri].size = ent[i].size; > + if (i == 0) > + continue; > + > + mr = &mem_map[DDR_REGION_INDEX(0)]; > + mem_map[ri].virt = mr->virt + mr->size; > + mem_map[ri].attrs = mr->attrs; > + } > + > + return 0; > +} > + > +int dram_init_banksize(void) > +{ > + struct draminfo_entry *ent = synquacer_draminfo->entry; > + int i; > + > + for (i = 0; i < ARRAY_SIZE(gd->bd->bi_dram); i++) { > + if (i < synquacer_draminfo->nr_regions) { > + debug("%s: dram[%d] = %llx@%llx\n", __func__, i, ent[i].size, ent[i].base); > + gd->bd->bi_dram[i].start = ent[i].base; > + gd->bd->bi_dram[i].size = ent[i].size; > + } > + } > + > + return 0; > +} > + > +int print_cpuinfo(void) > +{ > + printf("CPU: SC2A11:Cortex-A53 MPCore 24cores\n"); > + return 0; > +} > diff --git a/configs/synquacer_developerbox_defconfig b/configs/synquacer_developerbox_defconfig > new file mode 100644 > index 0000000000..c0d6fa49c0 > --- /dev/null > +++ b/configs/synquacer_developerbox_defconfig > @@ -0,0 +1,93 @@ > +CONFIG_ARM=y > +CONFIG_ARCH_SYNQUACER=y > +CONFIG_SYS_TEXT_BASE=0x08200000 > +CONFIG_ENV_SIZE=0x30000 > +CONFIG_ENV_OFFSET=0x300000 > +CONFIG_DEBUG_UART_BASE=0x2a400000 > +CONFIG_DEBUG_UART_CLOCK=62500000 > +CONFIG_ENV_SECT_SIZE=0x10000 > +CONFIG_DM_GPIO=y > +CONFIG_TARGET_DEVELOPERBOX=y > +CONFIG_DEFAULT_DEVICE_TREE="synquacer-sc2a11-developerbox" > +CONFIG_AHCI=y > +CONFIG_BOOTSTAGE_STASH_SIZE=4096 > +CONFIG_LOGLEVEL=9 > +CONFIG_LOG_MAX_LEVEL=7 > +CONFIG_HUSH_PARSER=y > +CONFIG_CMD_IMLS=y > +CONFIG_CMD_NVEDIT_INFO=y > +CONFIG_CMD_DM=y > +CONFIG_CMD_MII=y > +CONFIG_CMD_NET=y > +CONFIG_CMD_BOOTP=y > +CONFIG_CMD_DHCP=y > +CONFIG_CMD_PING=y > +CONFIG_CMD_GPT=y > +CONFIG_CMD_MMC=y > +CONFIG_CMD_MTD=y > +CONFIG_CMD_PART=y > +CONFIG_CMD_PCI=y > +CONFIG_CMD_POWEROFF=y > +CONFIG_CMD_SF=y > +CONFIG_CMD_SPI=y > +CONFIG_CMD_SATA=y > +CONFIG_CMD_NVME=y > +CONFIG_CMD_USB=y > +CONFIG_CMD_EXT2=y > +CONFIG_CMD_EXT4=y > +CONFIG_CMD_FAT=y > +CONFIG_CMD_MTDPARTS=y > +CONFIG_MTDPARTS_DEFAULT="nor1:448k(BootStrap-BL1),576k(Flash-Writer),512k(SCP-BL2),480k(FIP-TFA),32k(Stg2-Tables),1m@2m(U-Boot),1m@3m(UBoot-Env),2m@5m(Ex-OPTEE)" > +CONFIG_MTDIDS_DEFAULT="nor1=nor1" > +CONFIG_CMD_LOG=y > +CONFIG_PARTITION_TYPE_GUID=y > +CONFIG_OF_SEPARATE=y > +CONFIG_ENV_IS_IN_SPI_FLASH=y > +CONFIG_USE_ENV_SPI_BUS=y > +CONFIG_ENV_SPI_BUS=0 > +CONFIG_USE_ENV_SPI_CS=y > +CONFIG_ENV_SPI_CS=0 > +CONFIG_PROT_UDP=y > +CONFIG_BAUDRATE=115200 > +CONFIG_SPECIFY_CONSOLE_INDEX=y > +CONFIG_CONS_INDEX=0 > +CONFIG_DM_SERIAL=y > +CONFIG_PL01X_SERIAL=y > +CONFIG_SATA=y > +CONFIG_NVME=y > +CONFIG_SCSI_AHCI=y > +CONFIG_AHCI_PCI=y > +CONFIG_DM_MMC=y > +CONFIG_MMC_SDHCI=y > +CONFIG_F_SDH30_SDHCI=y > +CONFIG_MTD=y > +CONFIG_DM_MTD=y > +CONFIG_FLASH_CFI_DRIVER=y > +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y > +CONFIG_FLASH_CFI_MTD=y > +CONFIG_SYS_FLASH_CFI=y > +CONFIG_DM_SPI_FLASH=y > +CONFIG_SF_DEFAULT_SPEED=31250000 > +CONFIG_SPI_FLASH_MACRONIX=y > +CONFIG_SPI_FLASH_STMICRO=y > +CONFIG_SPI_FLASH_MTD=y > +CONFIG_PHYLIB=y > +CONFIG_PHYLIB_10G=y > +CONFIG_NET=y > +CONFIG_NETDEVICES=y > +CONFIG_SNI_NETSEC=y > +CONFIG_DM_ETH=y > +CONFIG_DM_MDIO=y > +CONFIG_PHY_GIGE=y > +CONFIG_RGMII=y > +CONFIG_MII=y > +CONFIG_SCSI=y > +CONFIG_DM_SCSI=y > +CONFIG_SPI=y > +CONFIG_DM_SPI=y > +CONFIG_SYNQUACER_SPI=y > +CONFIG_USB=y > +CONFIG_DM_USB=y > +CONFIG_USB_XHCI_HCD=y > +CONFIG_USB_XHCI_PCI=y > +CONFIG_USB_STORAGE=y > diff --git a/doc/board/index.rst b/doc/board/index.rst > index a70d2de19d..242372b321 100644 > --- a/doc/board/index.rst > +++ b/doc/board/index.rst > @@ -21,6 +21,7 @@ Board-specific doc > rockchip/index > sifive/index > sipeed/index > + socionext/index > st/index > tbs/index > toradex/index > diff --git a/doc/board/socionext/developerbox.rst b/doc/board/socionext/developerbox.rst > new file mode 100644 > index 0000000000..2d943c23be > --- /dev/null > +++ b/doc/board/socionext/developerbox.rst > @@ -0,0 +1,87 @@ > +.. SPDX-License-Identifier: GPL-2.0+ > + > +Introduction > +============ > + > +DeveloperBox is a certified 96boards Enterprise Edition board. The board/SoC has: - > + > +* Socionext SC2A11 24-cores ARM Cortex-A53 on tbe Mini-ATX form factor motherboard > +* 4 DIMM slots (4GB DDR4-2400 UDIMM shipped by default) > +* 1 4xPCIe Gen2 slot and 2 1xPCIe Gen2 slots > + (1x slots are connected via PCIe bridge chip) > +* 4 USB-3.0 ports > +* 2 SATA ports > +* 1 GbE network port > +* 1 USB-UART serial port (micro USB) > +* 64MB SPI NOR Flash > +* 8GB eMMC Flash Storage > +* 96boards LS connector > + > +The DeveloperBox schematic can be found here: - > +https://www.96boards.org/documentation/enterprise/developerbox/hardware-docs/mzsc2am_v03_20180115_a.pdf > + > +And the other documents can be found here: - > +https://www.96boards.org/documentation/enterprise/developerbox/ > + > + > +Currently, the U-Boot port supports: - > + > +* USB > +* eMMC > +* SPI-NOR > +* SATA > +* GbE > + > +The DeveloperBox boots the TF-A and EDK2 as a main bootloader by default. > +The DeveloperBox U-Boot port will replace the EDK2 and boot from TF-A as > +BL33, but no need to combine with it. > + > +Compile from source > +=================== > + > +You can build U-Boot without any additinal source code.:: > + > + cd u-boot > + export ARCH=arm64 > + export CROSS_COMPILE=aarch64-linux-gnu- > + make SynQuacer_defconfig > + make -j `noproc` > + > +Then, expand the binary to 1MB for preparing flash.:: > + > + cp u-boot.bin SPI_NOR_UBOOT.fd > + truncate -s 1M SPI_NOR_UBOOT.fd > + > +Installation > +============ > + > +You can install the SNI_NOR_UBOOT.fd via NOR flash writer. > + > +Flashing the U-Boot image on DeveloperBox requires a 96boards UART mezzanine or other mezzanine which can connect to LS-UART0 port. > +Connect USB cable from host to the LS-UART0 and set DSW2-7 to ON, and turn the board on again. The flash writer program will be started automatically; don’t forget to turn the DSW2-7 off again after flashing. > + > +*!!CAUTION!! If you failed to write the U-Boot image on wrong address, the board can be bricked. See below page if you need to recover the bricked board. See the following page for more detail* > + > +https://www.96boards.org/documentation/enterprise/developerbox/installation/board-recovery.md.html > + > +When the serial flasher is running correctly is will show the following boot messages shown via LS-UART0:: > + > + > + /*------------------------------------------*/ > + /* SC2A11 "SynQuacer" series Flash writer */ > + /* */ > + /* Version: cd254ac */ > + /* Build: 12/15/17 11:25:45 */ > + /*------------------------------------------*/ > + > + Command Input > > + > +Once the flasher tool is running we are ready flash the UEFI image:: > + > + flash rawwrite 200000 100000 > + >> Send SPI_NOR_UBOOT.fd via XMODEM (Control-A S in minicom) << > + > +*!!NOTE!! The flasher command parameter is different from the command for board recovery. U-Boot uses the offset 200000 (2-five-0, 2M in hex) and the size 100000 (1-five-0, 1M in hex).* > + > +After transferring the SPI_NOR_UBOOT.fd, turn off the DSW2-7 and reset the board. > + > diff --git a/doc/board/socionext/index.rst b/doc/board/socionext/index.rst > new file mode 100644 > index 0000000000..4673dcc45b > --- /dev/null > +++ b/doc/board/socionext/index.rst > @@ -0,0 +1,9 @@ > +.. SPDX-License-Identifier: GPL-2.0+ > + > +Socionext > +========= > + > +.. toctree:: > + :maxdepth: 2 > + > + developerbox > diff --git a/include/configs/synquacer.h b/include/configs/synquacer.h > new file mode 100644 > index 0000000000..b2dd6d0f0f > --- /dev/null > +++ b/include/configs/synquacer.h > @@ -0,0 +1,106 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * Copyright (C) 2016-2017 Socionext Inc. > + */ > +#ifndef __CONFIG_H > +#define __CONFIG_H > + > +/* Timers for fasp(TIMCLK) */ > +#define CONFIG_SYS_HZ 1000 /* 1 msec */ > +#define CONFIG_SYS_TIMERBASE 0x31080000 /* AP Timer 1 (ARM-SP804) */ > + > +/* > + * SDRAM (for initialize) > + */ > +#define CONFIG_SYS_SDRAM_BASE (0x80000000) /* Start address of DDR3 */ > +#define PHYS_SDRAM_SIZE (0x7c000000) /* Default size (2GB - Secure memory) */ > + > +#define CONFIG_VERY_BIG_RAM /* SynQuacer supports up to 64GB */ > +#define CONFIG_MAX_MEM_MAPPED PHYS_SDRAM_SIZE > + > +#define SQ_DRAMINFO_BASE (0x2e00ffc0) /* DRAM info from TF-A */ > + > +/* > + * Boot info > + */ > +#define CONFIG_SYS_INIT_SP_ADDR (0xe0000000) /* stack of init proccess */ > +#define CONFIG_SYS_MALLOC_LEN (0x01000000) /* 16Mbyte size of malloc() */ > +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE /* default kernel load address */ > + > +/* > + * Hardware drivers support > + */ > + > +/* Serial (pl011) */ > +#define UART_CLK (62500000) > +#define CONFIG_SERIAL_MULTI > +#define CONFIG_PL011_SERIAL > +#define CONFIG_PL011_CLOCK UART_CLK > +#define CONFIG_PL01x_PORTS {(void *)(0x2a400000)} > + > +#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ > + > +/* Support MTD */ > +#define CONFIG_SYS_MAX_FLASH_BANKS 1 > +#define CONFIG_SYS_FLASH_BASE (0x08000000) > +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} > + > +#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + (512 * 1024)) > +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + PHYS_SDRAM_SIZE) > + > +#define CONFIG_BAUDRATE 115200 > +#define CONFIG_SYS_BAUDRATE_TABLE {115200, 19200, 38400, 57600, 9600 } > + > +#define CONFIG_SYS_CBSIZE 1024 > +#define CONFIG_SYS_MAXARGS 128 > +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) > + > +/* Since U-Boot 64bit PCIe support is limited, disable 64bit MMIO support */ > +/* #define CONFIG_SYS_PCI_64BIT 1 */ > + > +/* Distro boot settings */ > +#ifndef CONFIG_SPL_BUILD > +#ifdef CONFIG_CMD_USB > +#define BOOT_TARGET_DEVICE_USB(func) func(USB, usb, 0) > +#else > +#define BOOT_TARGET_DEVICE_USB(func) > +#endif > + > +#ifdef CONFIG_CMD_MMC > +#define BOOT_TARGET_DEVICE_MMC(func) func(MMC, mmc, 0) > +#else > +#define BOOT_TARGET_DEVICE_MMC(func) > +#endif > + > +#ifdef CONFIG_CMD_NVME > +#define BOOT_TARGET_DEVICE_NVME(func) func(NVME, nvme, 0) > +#else > +#define BOOT_TARGET_DEVICE_NVME(func) > +#endif > + > +#ifdef CONFIG_CMD_SCSI > +#define BOOT_TARGET_DEVICE_SCSI(func) func(SCSI, scsi, 0) func(SCSI, scsi, 1) > +#else > +#define BOOT_TARGET_DEVICE_SCSI(func) > +#endif > + > +#define BOOT_TARGET_DEVICES(func) \ > + BOOT_TARGET_DEVICE_USB(func) \ > + BOOT_TARGET_DEVICE_MMC(func) \ > + BOOT_TARGET_DEVICE_SCSI(func) \ > + BOOT_TARGET_DEVICE_NVME(func) \ > + > +#include <config_distro_bootcmd.h> > +#else /* CONFIG_SPL_BUILD */ > +#define BOOTENV > +#endif > + > +#define CONFIG_EXTRA_ENV_SETTINGS \ > + "fdt_addr_r=0x9fe00000\0" \ > + "kernel_addr_r=0x90000000\0" \ > + "ramdisk_addr_r=0xa0000000\0" \ > + "scriptaddr=0x88000000\0" \ > + "pxefile_addr_r=0x88100000\0" \ > + BOOTENV > + > +#endif /* __CONFIG_H */ >
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index fba28323cd..1caea3ac58 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1675,6 +1675,20 @@ config ARCH_UNIPHIER Support for UniPhier SoC family developed by Socionext Inc. (formerly, System LSI Business Division of Panasonic Corporation) +config ARCH_SYNQUACER + bool "Socionext SynQuacer SoCs" + select ARM64 + select ONLY_GENERIC_GPIO + select DM + select GIC_V3 + select PSCI_RESET + select SYSRESET + select SYSRESET_PSCI + select OF_CONTROL + help + Support for SynQuacer SoC family developed by Socionext Inc. + This SoC is used on 96boards EE DeveloperBox. + config ARCH_STM32 bool "Support STMicroelectronics STM32 MCU with cortex M" select CPU_V7M @@ -2022,6 +2036,7 @@ source "board/hisilicon/poplar/Kconfig" source "board/isee/igep003x/Kconfig" source "board/kontron/sl28/Kconfig" source "board/myir/mys_6ulx/Kconfig" +source "board/socionext/developerbox/Kconfig" source "board/spear/spear300/Kconfig" source "board/spear/spear310/Kconfig" source "board/spear/spear320/Kconfig" diff --git a/board/socionext/developerbox/Kconfig b/board/socionext/developerbox/Kconfig new file mode 100644 index 0000000000..706b8dc0f1 --- /dev/null +++ b/board/socionext/developerbox/Kconfig @@ -0,0 +1,36 @@ +if ARCH_SYNQUACER + +choice + prompt "SC2A11 Cortex-A53 MPCore 24cores" + optional + +config TARGET_DEVELOPERBOX + bool "Socionext DeveloperBox" + select PCI + select DM_PCI + select PCIE_ECAM_SYNQUACER + select SYS_DISABLE_DCACHE_OPS + select OF_BOARD_SETUP + help + Choose this option if you build the U-Boot for the DeveloperBox + 96boards Enterprise Edition. + This board will booted from SCP firmware and it enables SMMU, thus + the dcache is updated automatically when DMA operation is executed. +endchoice + +config SYS_SOC + default "sc2a11" + +if TARGET_DEVELOPERBOX + +config SYS_BOARD + default "developerbox" + +config SYS_VENDOR + default "socionext" + +config SYS_CONFIG_NAME + default "synquacer" + +endif +endif diff --git a/board/socionext/developerbox/MAINTAINERS b/board/socionext/developerbox/MAINTAINERS new file mode 100644 index 0000000000..d10ad3b8f7 --- /dev/null +++ b/board/socionext/developerbox/MAINTAINERS @@ -0,0 +1,13 @@ +DEVELOPER BOX +M: Masami Hiramatsu <masami.hiramatsu@linaro.org> +M: Jassi Brar <jaswinder.singh@linaro.org> +S: Maintained +F: arch/arm/dts/synquacer-* +F: board/socionext/developerbox/* +F: configs/synquacer_developerbox_defconfig +F: drivers/mmc/f_sdh30.c +F: drivers/net/sni_netsec.c +F: drivers/pci/pcie_ecam_synquacer.c +F: drivers/spi/spi-synquacer.c +F: include/configs/synquacer.h +F: doc/board/socionext/developerbox.rst diff --git a/board/socionext/developerbox/Makefile b/board/socionext/developerbox/Makefile new file mode 100644 index 0000000000..4a46de995a --- /dev/null +++ b/board/socionext/developerbox/Makefile @@ -0,0 +1,9 @@ +# +# Author: Masami Hiramatsu <masami.hiramatsu@linaro.org> +# +# Copyright (C) 2021 Linaro Ltd. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := developerbox.o diff --git a/board/socionext/developerbox/developerbox.c b/board/socionext/developerbox/developerbox.c new file mode 100644 index 0000000000..3e943a279c --- /dev/null +++ b/board/socionext/developerbox/developerbox.c @@ -0,0 +1,145 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * u-boot/board/socionext/developerbox/developerbox.c + * + * Copyright (C) 2016-2017 Socionext Inc. + * Copyright (C) 2021 Linaro Ltd. + */ +#include <asm/types.h> +#include <asm/armv8/mmu.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <common.h> +#include <env_internal.h> +#include <fdt_support.h> +#include <log.h> + +static struct mm_region sc2a11_mem_map[] = { + { + .virt = 0x0UL, + .phys = 0x0UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_OUTER_SHARE + }, { + /* 1st DDR block */ + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = PHYS_SDRAM_SIZE, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE + }, { + /* 2nd DDR place holder */ + 0, + }, { + /* 3rd DDR place holder */ + 0, + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = sc2a11_mem_map; + +#define DDR_REGION_INDEX(i) (1 + (i)) +#define MAX_DDR_REGIONS 3 + +struct draminfo_entry { + u64 base; + u64 size; +}; + +struct draminfo { + u32 nr_regions; + u32 reserved; + struct draminfo_entry entry[3]; +}; + +struct draminfo *synquacer_draminfo = (void *)SQ_DRAMINFO_BASE; + +DECLARE_GLOBAL_DATA_PTR; + +#define LOAD_OFFSET 0x100 + +/* + * Miscellaneous platform dependent initialisations + */ +int board_init(void) +{ + gd->bd->bi_boot_params = CONFIG_SYS_LOAD_ADDR + LOAD_OFFSET; + + gd->env_addr = (ulong)&default_environment[0]; + + return 0; +} + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + /* Remove SPI NOR for making System DT compatible with EDK2 */ + fdt_del_node_and_alias(blob, "spi_nor"); + + return 0; +} + +/* + * DRAM configuration + */ + +int dram_init(void) +{ + struct draminfo_entry *ent = synquacer_draminfo->entry; + struct mm_region *mr; + int i, ri; + + if (synquacer_draminfo->nr_regions < 1) { + log_err("Failed to get correct DRAM information\n"); + return -1; + } + + /* + * U-Boot RAM size must be under the first DRAM region so that it doesn't + * access secure memory which is at the end of the first DRAM region. + */ + gd->ram_size = ent[0].size; + + /* Update memory region maps */ + for (i = 0; i < synquacer_draminfo->nr_regions; i++) { + if (i >= MAX_DDR_REGIONS) + break; + + ri = DDR_REGION_INDEX(i); + mem_map[ri].phys = ent[i].base; + mem_map[ri].size = ent[i].size; + if (i == 0) + continue; + + mr = &mem_map[DDR_REGION_INDEX(0)]; + mem_map[ri].virt = mr->virt + mr->size; + mem_map[ri].attrs = mr->attrs; + } + + return 0; +} + +int dram_init_banksize(void) +{ + struct draminfo_entry *ent = synquacer_draminfo->entry; + int i; + + for (i = 0; i < ARRAY_SIZE(gd->bd->bi_dram); i++) { + if (i < synquacer_draminfo->nr_regions) { + debug("%s: dram[%d] = %llx@%llx\n", __func__, i, ent[i].size, ent[i].base); + gd->bd->bi_dram[i].start = ent[i].base; + gd->bd->bi_dram[i].size = ent[i].size; + } + } + + return 0; +} + +int print_cpuinfo(void) +{ + printf("CPU: SC2A11:Cortex-A53 MPCore 24cores\n"); + return 0; +} diff --git a/configs/synquacer_developerbox_defconfig b/configs/synquacer_developerbox_defconfig new file mode 100644 index 0000000000..c0d6fa49c0 --- /dev/null +++ b/configs/synquacer_developerbox_defconfig @@ -0,0 +1,93 @@ +CONFIG_ARM=y +CONFIG_ARCH_SYNQUACER=y +CONFIG_SYS_TEXT_BASE=0x08200000 +CONFIG_ENV_SIZE=0x30000 +CONFIG_ENV_OFFSET=0x300000 +CONFIG_DEBUG_UART_BASE=0x2a400000 +CONFIG_DEBUG_UART_CLOCK=62500000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_DM_GPIO=y +CONFIG_TARGET_DEVELOPERBOX=y +CONFIG_DEFAULT_DEVICE_TREE="synquacer-sc2a11-developerbox" +CONFIG_AHCI=y +CONFIG_BOOTSTAGE_STASH_SIZE=4096 +CONFIG_LOGLEVEL=9 +CONFIG_LOG_MAX_LEVEL=7 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_IMLS=y +CONFIG_CMD_NVEDIT_INFO=y +CONFIG_CMD_DM=y +CONFIG_CMD_MII=y +CONFIG_CMD_NET=y +CONFIG_CMD_BOOTP=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_CMD_PART=y +CONFIG_CMD_PCI=y +CONFIG_CMD_POWEROFF=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_SATA=y +CONFIG_CMD_NVME=y +CONFIG_CMD_USB=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_MTDPARTS=y +CONFIG_MTDPARTS_DEFAULT="nor1:448k(BootStrap-BL1),576k(Flash-Writer),512k(SCP-BL2),480k(FIP-TFA),32k(Stg2-Tables),1m@2m(U-Boot),1m@3m(UBoot-Env),2m@5m(Ex-OPTEE)" +CONFIG_MTDIDS_DEFAULT="nor1=nor1" +CONFIG_CMD_LOG=y +CONFIG_PARTITION_TYPE_GUID=y +CONFIG_OF_SEPARATE=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_USE_ENV_SPI_BUS=y +CONFIG_ENV_SPI_BUS=0 +CONFIG_USE_ENV_SPI_CS=y +CONFIG_ENV_SPI_CS=0 +CONFIG_PROT_UDP=y +CONFIG_BAUDRATE=115200 +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_CONS_INDEX=0 +CONFIG_DM_SERIAL=y +CONFIG_PL01X_SERIAL=y +CONFIG_SATA=y +CONFIG_NVME=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y +CONFIG_DM_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_F_SDH30_SDHCI=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_FLASH_CFI_MTD=y +CONFIG_SYS_FLASH_CFI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_SPEED=31250000 +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_PHYLIB=y +CONFIG_PHYLIB_10G=y +CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_SNI_NETSEC=y +CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y +CONFIG_PHY_GIGE=y +CONFIG_RGMII=y +CONFIG_MII=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_SYNQUACER_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_PCI=y +CONFIG_USB_STORAGE=y diff --git a/doc/board/index.rst b/doc/board/index.rst index a70d2de19d..242372b321 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -21,6 +21,7 @@ Board-specific doc rockchip/index sifive/index sipeed/index + socionext/index st/index tbs/index toradex/index diff --git a/doc/board/socionext/developerbox.rst b/doc/board/socionext/developerbox.rst new file mode 100644 index 0000000000..2d943c23be --- /dev/null +++ b/doc/board/socionext/developerbox.rst @@ -0,0 +1,87 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Introduction +============ + +DeveloperBox is a certified 96boards Enterprise Edition board. The board/SoC has: - + +* Socionext SC2A11 24-cores ARM Cortex-A53 on tbe Mini-ATX form factor motherboard +* 4 DIMM slots (4GB DDR4-2400 UDIMM shipped by default) +* 1 4xPCIe Gen2 slot and 2 1xPCIe Gen2 slots + (1x slots are connected via PCIe bridge chip) +* 4 USB-3.0 ports +* 2 SATA ports +* 1 GbE network port +* 1 USB-UART serial port (micro USB) +* 64MB SPI NOR Flash +* 8GB eMMC Flash Storage +* 96boards LS connector + +The DeveloperBox schematic can be found here: - +https://www.96boards.org/documentation/enterprise/developerbox/hardware-docs/mzsc2am_v03_20180115_a.pdf + +And the other documents can be found here: - +https://www.96boards.org/documentation/enterprise/developerbox/ + + +Currently, the U-Boot port supports: - + +* USB +* eMMC +* SPI-NOR +* SATA +* GbE + +The DeveloperBox boots the TF-A and EDK2 as a main bootloader by default. +The DeveloperBox U-Boot port will replace the EDK2 and boot from TF-A as +BL33, but no need to combine with it. + +Compile from source +=================== + +You can build U-Boot without any additinal source code.:: + + cd u-boot + export ARCH=arm64 + export CROSS_COMPILE=aarch64-linux-gnu- + make SynQuacer_defconfig + make -j `noproc` + +Then, expand the binary to 1MB for preparing flash.:: + + cp u-boot.bin SPI_NOR_UBOOT.fd + truncate -s 1M SPI_NOR_UBOOT.fd + +Installation +============ + +You can install the SNI_NOR_UBOOT.fd via NOR flash writer. + +Flashing the U-Boot image on DeveloperBox requires a 96boards UART mezzanine or other mezzanine which can connect to LS-UART0 port. +Connect USB cable from host to the LS-UART0 and set DSW2-7 to ON, and turn the board on again. The flash writer program will be started automatically; don’t forget to turn the DSW2-7 off again after flashing. + +*!!CAUTION!! If you failed to write the U-Boot image on wrong address, the board can be bricked. See below page if you need to recover the bricked board. See the following page for more detail* + +https://www.96boards.org/documentation/enterprise/developerbox/installation/board-recovery.md.html + +When the serial flasher is running correctly is will show the following boot messages shown via LS-UART0:: + + + /*------------------------------------------*/ + /* SC2A11 "SynQuacer" series Flash writer */ + /* */ + /* Version: cd254ac */ + /* Build: 12/15/17 11:25:45 */ + /*------------------------------------------*/ + + Command Input > + +Once the flasher tool is running we are ready flash the UEFI image:: + + flash rawwrite 200000 100000 + >> Send SPI_NOR_UBOOT.fd via XMODEM (Control-A S in minicom) << + +*!!NOTE!! The flasher command parameter is different from the command for board recovery. U-Boot uses the offset 200000 (2-five-0, 2M in hex) and the size 100000 (1-five-0, 1M in hex).* + +After transferring the SPI_NOR_UBOOT.fd, turn off the DSW2-7 and reset the board. + diff --git a/doc/board/socionext/index.rst b/doc/board/socionext/index.rst new file mode 100644 index 0000000000..4673dcc45b --- /dev/null +++ b/doc/board/socionext/index.rst @@ -0,0 +1,9 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Socionext +========= + +.. toctree:: + :maxdepth: 2 + + developerbox diff --git a/include/configs/synquacer.h b/include/configs/synquacer.h new file mode 100644 index 0000000000..b2dd6d0f0f --- /dev/null +++ b/include/configs/synquacer.h @@ -0,0 +1,106 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2016-2017 Socionext Inc. + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +/* Timers for fasp(TIMCLK) */ +#define CONFIG_SYS_HZ 1000 /* 1 msec */ +#define CONFIG_SYS_TIMERBASE 0x31080000 /* AP Timer 1 (ARM-SP804) */ + +/* + * SDRAM (for initialize) + */ +#define CONFIG_SYS_SDRAM_BASE (0x80000000) /* Start address of DDR3 */ +#define PHYS_SDRAM_SIZE (0x7c000000) /* Default size (2GB - Secure memory) */ + +#define CONFIG_VERY_BIG_RAM /* SynQuacer supports up to 64GB */ +#define CONFIG_MAX_MEM_MAPPED PHYS_SDRAM_SIZE + +#define SQ_DRAMINFO_BASE (0x2e00ffc0) /* DRAM info from TF-A */ + +/* + * Boot info + */ +#define CONFIG_SYS_INIT_SP_ADDR (0xe0000000) /* stack of init proccess */ +#define CONFIG_SYS_MALLOC_LEN (0x01000000) /* 16Mbyte size of malloc() */ +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE /* default kernel load address */ + +/* + * Hardware drivers support + */ + +/* Serial (pl011) */ +#define UART_CLK (62500000) +#define CONFIG_SERIAL_MULTI +#define CONFIG_PL011_SERIAL +#define CONFIG_PL011_CLOCK UART_CLK +#define CONFIG_PL01x_PORTS {(void *)(0x2a400000)} + +#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ + +/* Support MTD */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_FLASH_BASE (0x08000000) +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} + +#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + (512 * 1024)) +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + PHYS_SDRAM_SIZE) + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {115200, 19200, 38400, 57600, 9600 } + +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SYS_MAXARGS 128 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* Since U-Boot 64bit PCIe support is limited, disable 64bit MMIO support */ +/* #define CONFIG_SYS_PCI_64BIT 1 */ + +/* Distro boot settings */ +#ifndef CONFIG_SPL_BUILD +#ifdef CONFIG_CMD_USB +#define BOOT_TARGET_DEVICE_USB(func) func(USB, usb, 0) +#else +#define BOOT_TARGET_DEVICE_USB(func) +#endif + +#ifdef CONFIG_CMD_MMC +#define BOOT_TARGET_DEVICE_MMC(func) func(MMC, mmc, 0) +#else +#define BOOT_TARGET_DEVICE_MMC(func) +#endif + +#ifdef CONFIG_CMD_NVME +#define BOOT_TARGET_DEVICE_NVME(func) func(NVME, nvme, 0) +#else +#define BOOT_TARGET_DEVICE_NVME(func) +#endif + +#ifdef CONFIG_CMD_SCSI +#define BOOT_TARGET_DEVICE_SCSI(func) func(SCSI, scsi, 0) func(SCSI, scsi, 1) +#else +#define BOOT_TARGET_DEVICE_SCSI(func) +#endif + +#define BOOT_TARGET_DEVICES(func) \ + BOOT_TARGET_DEVICE_USB(func) \ + BOOT_TARGET_DEVICE_MMC(func) \ + BOOT_TARGET_DEVICE_SCSI(func) \ + BOOT_TARGET_DEVICE_NVME(func) \ + +#include <config_distro_bootcmd.h> +#else /* CONFIG_SPL_BUILD */ +#define BOOTENV +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_addr_r=0x9fe00000\0" \ + "kernel_addr_r=0x90000000\0" \ + "ramdisk_addr_r=0xa0000000\0" \ + "scriptaddr=0x88000000\0" \ + "pxefile_addr_r=0x88100000\0" \ + BOOTENV + +#endif /* __CONFIG_H */
Add the DeveloperBox 96boards EE support. This board is also known as Socionext SynQuacer E-Series. It contians one "SC2A11" SoC, which has 24-cores of arm Cortex-A53, and 4 DDR3 slots, 3 PCIe slots (1 4x port and 2 1x ports which are expanded via PCIe bridge chip), 2 USB 3.0 ports and 2 USB 2.0 ports, 2 SATA ports and 1 GbE, 64MB NOR flash and 8GB eMMC on standard MicroATX Form Factor. For more information, see this page; https://www.96boards.org/product/developerbox/ Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org> --- Changes in v2: - Do not include arch/gpio.h and remove arch-sc2a11/gpio.h. - Remove non-UEFI boot commands. - Use Distro boot. - Remove NOR-connected SPI node by path instead of alias. - Rename configs/SynQuacer_defconfig to configs/synquacer_developerbox_defconfig. - Rename include/configs/SynQuacer.h to include/configs/synquacer.h. - Move README under doc/board/socionext/ and make it .rst text. --- arch/arm/Kconfig | 15 +++ board/socionext/developerbox/Kconfig | 36 +++++++ board/socionext/developerbox/MAINTAINERS | 13 ++ board/socionext/developerbox/Makefile | 9 ++ board/socionext/developerbox/developerbox.c | 145 +++++++++++++++++++++++++++ configs/synquacer_developerbox_defconfig | 93 +++++++++++++++++ doc/board/index.rst | 1 doc/board/socionext/developerbox.rst | 87 ++++++++++++++++ doc/board/socionext/index.rst | 9 ++ include/configs/synquacer.h | 106 ++++++++++++++++++++ 10 files changed, 514 insertions(+) create mode 100644 board/socionext/developerbox/Kconfig create mode 100644 board/socionext/developerbox/MAINTAINERS create mode 100644 board/socionext/developerbox/Makefile create mode 100644 board/socionext/developerbox/developerbox.c create mode 100644 configs/synquacer_developerbox_defconfig create mode 100644 doc/board/socionext/developerbox.rst create mode 100644 doc/board/socionext/index.rst create mode 100644 include/configs/synquacer.h