diff mbox series

mips: mt7628: fix ddr_type for MT7688KN

Message ID 1614064364-30544-1-git-send-email-weijie.gao@mediatek.com
State New
Delegated to: Daniel Schwierzeck
Headers show
Series mips: mt7628: fix ddr_type for MT7688KN | expand

Commit Message

Weijie Gao Feb. 23, 2021, 7:12 a.m. UTC
The MT7688KN is a multi-chip package with 8MiB DDR1 KGD. So the DDR type
from bootstrap register must be ignored, and always be assumed as DDR1.

This patch fixes an issue that mt7628_ddr_pad_ldo_config() may be passed
with a wrong ddr_type in MT7688KN.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
 arch/mips/mach-mtmips/mt7628/ddr.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

Comments

Stefan Roese Feb. 26, 2021, 11:23 a.m. UTC | #1
Hi Weijie,

On 23.02.21 08:12, Weijie Gao wrote:
> The MT7688KN is a multi-chip package with 8MiB DDR1 KGD. So the DDR type
> from bootstrap register must be ignored, and always be assumed as DDR1.
> 
> This patch fixes an issue that mt7628_ddr_pad_ldo_config() may be passed
> with a wrong ddr_type in MT7688KN.
> 
> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
> ---
>   arch/mips/mach-mtmips/mt7628/ddr.c | 6 +++---
>   1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/mips/mach-mtmips/mt7628/ddr.c b/arch/mips/mach-mtmips/mt7628/ddr.c
> index b091f2ecff..4e72459906 100644
> --- a/arch/mips/mach-mtmips/mt7628/ddr.c
> +++ b/arch/mips/mach-mtmips/mt7628/ddr.c
> @@ -140,6 +140,9 @@ void mt7628_ddr_init(void)
>   	lspd = readl(sysc + SYSCTL_CLKCFG0_REG) &
>   	       (CPU_PLL_FROM_BBP | CPU_PLL_FROM_XTAL);
>   
> +	if (pkg_type == PKG_ID_KN)
> +		ddr_type = DRAM_DDR1;
> +
>   	mt7628_memc_reset(1);
>   	__udelay(200);
>   
> @@ -152,9 +155,6 @@ void mt7628_ddr_init(void)
>   	param.memsize = 0;
>   	param.bus_width = 0;
>   
> -	if (pkg_type == PKG_ID_KN)
> -		ddr_type = DRAM_DDR1;
> -
>   	if (ddr_type == DRAM_DDR1) {
>   		if (lspd)
>   			param.cfgs = ddr1_cfgs_160mhz;
> 

Reviewed-by: Stefan Roese <sr@denx.de>

Just out of interest. How did you spot this issue?

Thanks,
Stefan
diff mbox series

Patch

diff --git a/arch/mips/mach-mtmips/mt7628/ddr.c b/arch/mips/mach-mtmips/mt7628/ddr.c
index b091f2ecff..4e72459906 100644
--- a/arch/mips/mach-mtmips/mt7628/ddr.c
+++ b/arch/mips/mach-mtmips/mt7628/ddr.c
@@ -140,6 +140,9 @@  void mt7628_ddr_init(void)
 	lspd = readl(sysc + SYSCTL_CLKCFG0_REG) &
 	       (CPU_PLL_FROM_BBP | CPU_PLL_FROM_XTAL);
 
+	if (pkg_type == PKG_ID_KN)
+		ddr_type = DRAM_DDR1;
+
 	mt7628_memc_reset(1);
 	__udelay(200);
 
@@ -152,9 +155,6 @@  void mt7628_ddr_init(void)
 	param.memsize = 0;
 	param.bus_width = 0;
 
-	if (pkg_type == PKG_ID_KN)
-		ddr_type = DRAM_DDR1;
-
 	if (ddr_type == DRAM_DDR1) {
 		if (lspd)
 			param.cfgs = ddr1_cfgs_160mhz;