| Message ID | 1613663886-83811-30-git-send-email-bmeng.cn@gmail.com |
|---|---|
| State | Superseded |
| Delegated to: | Priyanka Jain |
| Headers | show |
| Series | ppc: qemu: Convert qemu-ppce500 to driver model and enable additional driver support | expand |
>-----Original Message----- >From: Bin Meng <bmeng.cn@gmail.com> >Sent: Thursday, February 18, 2021 9:28 PM >To: Simon Glass <sjg@chromium.org>; Alexander Graf <agraf@csgraf.de>; >Priyanka Jain <priyanka.jain@nxp.com> >Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Tom Rini ><trini@konsulko.com> >Subject: [PATCH v2 29/38] gpio: mpc8xxx: Support controller register physical >address beyond 32-bit > >dev_read_addr_size_index() returns fdt_addr_t which might be a 64-bit >physical address. This might be true for some 85xx SoCs whose CCSBAR is >mapped beyond 4 GiB. > >Signed-off-by: Bin Meng <bmeng.cn@gmail.com> > >--- > >Changes in v2: >- new patch: gpio: mpc8xxx: Support controller register physical address >beyond 32-bit > > arch/powerpc/include/asm/arch-mpc85xx/gpio.h | 2 +- > drivers/gpio/mpc8xxx_gpio.c | 7 ++++--- > 2 files changed, 5 insertions(+), 4 deletions(-) > Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
diff --git a/arch/powerpc/include/asm/arch-mpc85xx/gpio.h b/arch/powerpc/include/asm/arch-mpc85xx/gpio.h index c7086a8..79ba786 100644 --- a/arch/powerpc/include/asm/arch-mpc85xx/gpio.h +++ b/arch/powerpc/include/asm/arch-mpc85xx/gpio.h @@ -18,7 +18,7 @@ #endif struct mpc8xxx_gpio_plat { - ulong addr; + phys_addr_t addr; unsigned long size; uint ngpios; }; diff --git a/drivers/gpio/mpc8xxx_gpio.c b/drivers/gpio/mpc8xxx_gpio.c index c733603..f7ffd89 100644 --- a/drivers/gpio/mpc8xxx_gpio.c +++ b/drivers/gpio/mpc8xxx_gpio.c @@ -20,7 +20,7 @@ struct mpc8xxx_gpio_data { /* The bank's register base in memory */ struct ccsr_gpio __iomem *base; /* The address of the registers; used to identify the bank */ - ulong addr; + phys_addr_t addr; /* The GPIO count of the bank */ uint gpio_count; /* The GPDAT register cannot be used to determine the value of output @@ -181,7 +181,7 @@ static int mpc8xxx_gpio_of_to_plat(struct udevice *dev) if (dev_read_bool(dev, "little-endian")) data->little_endian = true; - plat->addr = (ulong)dev_read_addr_size_index(dev, 0, (fdt_size_t *)&plat->size); + plat->addr = dev_read_addr_size_index(dev, 0, (fdt_size_t *)&plat->size); plat->ngpios = dev_read_u32_default(dev, "ngpios", 32); return 0; @@ -220,7 +220,8 @@ static int mpc8xxx_gpio_probe(struct udevice *dev) mpc8xxx_gpio_plat_to_priv(dev); - snprintf(name, sizeof(name), "MPC@%lx_", data->addr); + snprintf(name, sizeof(name), "MPC@%.8llx", + (unsigned long long)data->addr); str = strdup(name); if (!str)
dev_read_addr_size_index() returns fdt_addr_t which might be a 64-bit physical address. This might be true for some 85xx SoCs whose CCSBAR is mapped beyond 4 GiB. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> --- Changes in v2: - new patch: gpio: mpc8xxx: Support controller register physical address beyond 32-bit arch/powerpc/include/asm/arch-mpc85xx/gpio.h | 2 +- drivers/gpio/mpc8xxx_gpio.c | 7 ++++--- 2 files changed, 5 insertions(+), 4 deletions(-)