From patchwork Fri Oct 16 07:36:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?V2VpamllIEdhbyAo6auY5oOf5p2wKQ==?= X-Patchwork-Id: 1383153 X-Patchwork-Delegate: daniel.schwierzeck@googlemail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=mediatek.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=mediatek.com header.i=@mediatek.com header.a=rsa-sha256 header.s=dk header.b=bHgnzoyP; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4CCJ0057d4z9sTL for ; Fri, 16 Oct 2020 18:37:36 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 1DEDB8242B; Fri, 16 Oct 2020 09:36:27 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=mediatek.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=mediatek.com header.i=@mediatek.com header.b="bHgnzoyP"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 89BEF82396; Fri, 16 Oct 2020 09:36:24 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=0.5 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MIME_BASE64_TEXT,RDNS_NONE,SPF_HELO_NONE, UNPARSEABLE_RELAY,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.2 Received: from mailgw02.mediatek.com (unknown [1.203.163.81]) by phobos.denx.de (Postfix) with ESMTP id 6466A82369 for ; Fri, 16 Oct 2020 09:36:21 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=mediatek.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=weijie.gao@mediatek.com X-UUID: aafc96743bc947fbacc74e4ecf9cca34-20201016 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:Message-ID:Date:Subject:CC:To:From; bh=4xiJzEoObSef6SVj3ok7BXm9d5S6f/B6jQ3wOuzJoaE=; b=bHgnzoyPveLlKLnOGlgreU7WteQTUdjnZmmBSu4F9hbl/spGiwRFfLyooFzoZEGlwrJc0nW5JUL+KX20iQUEZtwDykanPplGH7Fy5uQ26jxjrMEZesf4KTEc1k3DL75XaZw+bEHBaOvCdhZb21v/iEsEe/L0/qFj7KbJk8m4//A=; X-UUID: aafc96743bc947fbacc74e4ecf9cca34-20201016 Received: from mtkcas35.mediatek.inc [(172.27.4.253)] by mailgw02.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1963787621; Fri, 16 Oct 2020 15:36:08 +0800 Received: from MTKCAS32.mediatek.inc (172.27.4.184) by MTKMBS31N1.mediatek.inc (172.27.4.69) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 16 Oct 2020 15:36:06 +0800 Received: from mcddlt001.mediatek.inc (10.19.240.15) by MTKCAS32.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 16 Oct 2020 15:36:06 +0800 From: Weijie Gao To: CC: GSS_MTK_Uboot_upstream , Daniel Schwierzeck , Stefan Roese , Stefan Roese , Stefan Roese , Lukasz Majewski , Weijie Gao Subject: [PATCH 09/18] clk: add clock driver for MediaTek MT7620 SoC Date: Fri, 16 Oct 2020 15:36:05 +0800 Message-ID: <1602833765-19414-1-git-send-email-weijie.gao@mediatek.com> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 X-TM-SNTS-SMTP: D9C7761BD2F446E5DFBC241D0EA820D98B47E09069F2E4484CF319B5106FC3242000:8 X-MTK: N X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean This patch adds a clock driver for MediaTek MT7620 SoC. This driver provides clock gate control as well as getting clock frequency for CPU/SYS/XTAL and some peripherals. Signed-off-by: Weijie Gao --- drivers/clk/mtmips/Makefile | 1 + drivers/clk/mtmips/clk-mt7620.c | 154 +++++++++++++++++++++++++ include/dt-bindings/clock/mt7620-clk.h | 40 +++++++ 3 files changed, 195 insertions(+) create mode 100644 drivers/clk/mtmips/clk-mt7620.c create mode 100644 include/dt-bindings/clock/mt7620-clk.h diff --git a/drivers/clk/mtmips/Makefile b/drivers/clk/mtmips/Makefile index e1938418da..732e7f2545 100644 --- a/drivers/clk/mtmips/Makefile +++ b/drivers/clk/mtmips/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_SOC_MT7620) += clk-mt7620.o obj-$(CONFIG_SOC_MT7628) += clk-mt7628.o diff --git a/drivers/clk/mtmips/clk-mt7620.c b/drivers/clk/mtmips/clk-mt7620.c new file mode 100644 index 0000000000..8cbf7e8579 --- /dev/null +++ b/drivers/clk/mtmips/clk-mt7620.c @@ -0,0 +1,154 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 MediaTek Inc. All Rights Reserved. + * + * Author: Weijie Gao + */ + +#include +#include +#include +#include +#include + +/* CLKCFG1 */ +#define CLKCFG1_REG 0x30 + +#define CLK_SRC_CPU -1 +#define CLK_SRC_CPU_D2 -2 +#define CLK_SRC_SYS -3 +#define CLK_SRC_XTAL -4 +#define CLK_SRC_PERI -5 + +struct mt7620_clk_priv { + struct udevice *sysc; + struct mt7620_sysc_clks clks; +}; + +static const int mt7620_clks[] = { + [CLK_SYS] = CLK_SRC_SYS, + [CLK_CPU] = CLK_SRC_CPU, + [CLK_XTAL] = CLK_SRC_XTAL, + [CLK_MIPS_CNT] = CLK_SRC_CPU_D2, + [CLK_UARTF] = CLK_SRC_PERI, + [CLK_UARTL] = CLK_SRC_PERI, + [CLK_SPI] = CLK_SRC_SYS, + [CLK_I2C] = CLK_SRC_PERI, + [CLK_I2S] = CLK_SRC_PERI, +}; + +static ulong mt7620_clk_get_rate(struct clk *clk) +{ + struct mt7620_clk_priv *priv = dev_get_priv(clk->dev); + + if (clk->id >= ARRAY_SIZE(mt7620_clks)) + return 0; + + switch (mt7620_clks[clk->id]) { + case CLK_SRC_CPU: + return priv->clks.cpu_clk; + case CLK_SRC_CPU_D2: + return priv->clks.cpu_clk / 2; + case CLK_SRC_SYS: + return priv->clks.sys_clk; + case CLK_SRC_XTAL: + return priv->clks.xtal_clk; + case CLK_SRC_PERI: + return priv->clks.peri_clk; + default: + return mt7620_clks[clk->id]; + } +} + +static int mt7620_clkcfg1_rmw(struct mt7620_clk_priv *priv, u32 clr, u32 set) +{ + u32 val; + int ret; + + ret = misc_read(priv->sysc, CLKCFG1_REG, &val, sizeof(val)); + if (ret) { + dev_err(dev, "mt7620_clk: failed to read CLKCFG1\n"); + return ret; + } + + val &= ~clr; + val |= set; + + ret = misc_write(priv->sysc, CLKCFG1_REG, &val, sizeof(val)); + if (ret) { + dev_err(dev, "mt7620_clk: failed to write CLKCFG1\n"); + return ret; + } + + return 0; +} + +static int mt7620_clk_enable(struct clk *clk) +{ + struct mt7620_clk_priv *priv = dev_get_priv(clk->dev); + + if (clk->id > 30) + return -1; + + return mt7620_clkcfg1_rmw(priv, 0, BIT(clk->id)); +} + +static int mt7620_clk_disable(struct clk *clk) +{ + struct mt7620_clk_priv *priv = dev_get_priv(clk->dev); + + if (clk->id > 30) + return -1; + + return mt7620_clkcfg1_rmw(priv, BIT(clk->id), 0); +} + +const struct clk_ops mt7620_clk_ops = { + .enable = mt7620_clk_enable, + .disable = mt7620_clk_disable, + .get_rate = mt7620_clk_get_rate, +}; + +static int mt7620_clk_probe(struct udevice *dev) +{ + struct mt7620_clk_priv *priv = dev_get_priv(dev); + struct ofnode_phandle_args sysc_args; + int ret; + + ret = ofnode_parse_phandle_with_args(dev->node, "mediatek,sysc", NULL, + 0, 0, &sysc_args); + if (ret) { + dev_err(dev, "mt7620_clk: sysc property not found\n"); + return ret; + } + + ret = uclass_get_device_by_ofnode(UCLASS_MISC, sysc_args.node, + &priv->sysc); + if (ret) { + dev_err(dev, "mt7620_clk: failed to sysc device\n"); + return ret; + } + + ret = misc_ioctl(priv->sysc, MT7620_SYSC_IOCTL_GET_CLK, + &priv->clks); + if (ret) { + dev_err(dev, "mt7620_clk: failed to get base clocks\n"); + return ret; + } + + return 0; +} + +static const struct udevice_id mt7620_clk_ids[] = { + { .compatible = "mediatek,mt7620-clk" }, + { } +}; + +U_BOOT_DRIVER(mt7620_clk) = { + .name = "mt7620-clk", + .id = UCLASS_CLK, + .of_match = mt7620_clk_ids, + .probe = mt7620_clk_probe, + .priv_auto_alloc_size = sizeof(struct mt7620_clk_priv), + .ops = &mt7620_clk_ops, +}; diff --git a/include/dt-bindings/clock/mt7620-clk.h b/include/dt-bindings/clock/mt7620-clk.h new file mode 100644 index 0000000000..3bb91ebdf1 --- /dev/null +++ b/include/dt-bindings/clock/mt7620-clk.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020 MediaTek Inc. + * + * Author: Weijie Gao + */ + +#ifndef _DT_BINDINGS_MT7620_CLK_H_ +#define _DT_BINDINGS_MT7620_CLK_H_ + +/* Base clocks */ +#define CLK_SYS 34 +#define CLK_CPU 33 +#define CLK_XTAL 32 + +/* Peripheral clocks */ +#define CLK_SDHC 30 +#define CLK_MIPS_CNT 28 +#define CLK_PCIE 26 +#define CLK_UPHY_12M 25 +#define CLK_EPHY 24 +#define CLK_ESW 23 +#define CLK_UPHY_48M 22 +#define CLK_FE 21 +#define CLK_UARTL 19 +#define CLK_SPI 18 +#define CLK_I2S 17 +#define CLK_I2C 16 +#define CLK_NAND 15 +#define CLK_GDMA 14 +#define CLK_PIO 13 +#define CLK_UARTF 12 +#define CLK_PCM 11 +#define CLK_MC 10 +#define CLK_INTC 9 +#define CLK_TIMER 8 +#define CLK_GE2 7 +#define CLK_GE1 6 + +#endif /* _DT_BINDINGS_MT7620_CLK_H_ */