diff mbox series

[v2,11/12] pci: layerscape: Add size check for config resource

Message ID 1601290574-20151-12-git-send-email-wasim.khan@nxp.com
State Accepted
Commit 49df7c90867c0a991222f6a4eac8e42879880c23
Delegated to: Priyanka Jain
Headers show
Series Add label to pcie nodes | expand

Commit Message

Wasim Khan Sept. 28, 2020, 10:56 a.m. UTC 
resource "config" is required to have minimum 8KB space
as per hardware documentation.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
---
Changes in V2:
- Updated commit description
- Fix CheckPatch issue

Changes in V3:
- Fix compilation issue with ls102xa platforms

 drivers/pci/pcie_layerscape_rc.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/drivers/pci/pcie_layerscape_rc.c b/drivers/pci/pcie_layerscape_rc.c
index f9e3089..cdfcad6 100644
--- a/drivers/pci/pcie_layerscape_rc.c
+++ b/drivers/pci/pcie_layerscape_rc.c
@@ -314,6 +314,13 @@  static int ls_pcie_probe(struct udevice *dev)
 		return ret;
 	}
 
+	cfg_size = fdt_resource_size(&pcie_rc->cfg_res);
+	if (cfg_size < SZ_8K) {
+		printf("PCIe%d: %s Invalid size(0x%llx) for resource \"config\",expected minimum 0x%x\n",
+		       PCIE_SRDS_PRTCL(pcie->idx), dev->name, (u64)cfg_size, SZ_8K);
+		return 0;
+	}
+
 	/*
 	 * Fix the pcie memory map address and PF control registers address
 	 * for LS2088A series SoCs
@@ -323,7 +330,6 @@  static int ls_pcie_probe(struct udevice *dev)
 	if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
 	    svr == SVR_LS2048A || svr == SVR_LS2044A ||
 	    svr == SVR_LS2081A || svr == SVR_LS2041A) {
-		cfg_size = fdt_resource_size(&pcie_rc->cfg_res);
 		pcie_rc->cfg_res.start = LS2088A_PCIE1_PHYS_ADDR +
 					 LS2088A_PCIE_PHYS_SIZE * pcie->idx;
 		pcie_rc->cfg_res.end = pcie_rc->cfg_res.start + cfg_size;