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Fri, 26 Jun 2020 12:39:39 +0000 From: Sagar Shrikant Kadam To: u-boot@lists.denx.de Cc: rick@andestech.com, bin.meng@windriver.com, jagan@amarulasolutions.com, pragnesh.patel@sifive.com, anup.patel@wdc.com, sjg@chromium.org, ye.li@nxp.com, peng.fan@nxp.com, seanga2@gmail.com, Sagar Shrikant Kadam Subject: [PATCH v6 3/4] riscv: cpu: correctly handle the setting of CPU_FEAT_MMU bit Date: Fri, 26 Jun 2020 05:39:20 -0700 Message-Id: <1593175161-26278-4-git-send-email-sagar.kadam@sifive.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1593175161-26278-1-git-send-email-sagar.kadam@sifive.com> References: <1593175161-26278-1-git-send-email-sagar.kadam@sifive.com> X-ClientProxiedBy: BY3PR05CA0027.namprd05.prod.outlook.com (2603:10b6:a03:254::32) To BN8PR13MB2611.namprd13.prod.outlook.com (2603:10b6:408:81::17) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from gamma07.internal.sifive.com (64.62.193.194) by BY3PR05CA0027.namprd05.prod.outlook.com (2603:10b6:a03:254::32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.20.3131.12 via Frontend Transport; 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DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData: A4jgwX1aFQp73rTxLqgCxPBpesFCKANjyjdPbBwG4H+qcVDXY/iS0Od0qolo0VDzeTN96O8/29JFzv7/mlvjSs5JxgQQ+SxagvC0gmw0FfZNfYwpguHjLEGPo8PLnIx+socCzq0Tqxw5dW9tfWxdbb0zGhRGojjkBKvi/AUeIjesVMhY/ixoU1JcSzKwNRKaKTAS8JcQPhvEaK7R0V+209IfEk3eCswStoOrcMwkLqJg1A81OUKFSlbzXdv+OrU+oHvmTIPITh6CZPq7ExV+gp+TGPnJGm53xXPnNZ8IrP0mhE7XLnmYoBgK+SlBcvIfa1I4B9HAPkjmQ98KMCpCCyBjHy5D+xD/ASIKq4da4Q2imc36lU2RKYqWCAMduAHZPFetS8NPPnZGJLXMCuuRA9h81y1SExR4/jANp0GIo2cW49Mx6jRvNHH3fFB3M2B/+DhOHLKFTdpdne4yBiHQXnaY3vMMa5JzMosbiV7G/hI= X-OriginatorOrg: sifive.com X-MS-Exchange-CrossTenant-Network-Message-Id: bd6c8b09-32f0-4d96-39a9-08d819cdfdaf X-MS-Exchange-CrossTenant-AuthSource: BN8PR13MB2611.namprd13.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Jun 2020 12:39:39.0872 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 22f88e9d-ae0d-4ed9-b984-cdc9be1529f1 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: v8nY5FBbrom4BDXKCpEZbLT4g8PUYvYIZiEEKc7j6RN+4F3xB3HdJZhIhFnKjt7MEvk3SCq7LuS+1odtGwZ64A== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR13MB1651 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.30rc1 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de X-Virus-Status: Clean The conditional check to read "mmu-type" from the device tree is not rightly handled due to which the cpu feature doesn't include CPU_FEAT_MMU even if it's corresponding entry is present in the device tree. The initialization of cpu features is now taken care in cpu-uclass driver, so no need to zero out cpu_freq in riscv_cpu driver and can be removed. Signed-off-by: Sagar Shrikant Kadam Reviewed-by: Pragnesh Patel Reviewed-by: Bin Meng --- drivers/cpu/riscv_cpu.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/cpu/riscv_cpu.c b/drivers/cpu/riscv_cpu.c index 76b0489..112690f 100644 --- a/drivers/cpu/riscv_cpu.c +++ b/drivers/cpu/riscv_cpu.c @@ -36,9 +36,6 @@ static int riscv_cpu_get_info(struct udevice *dev, struct cpu_info *info) struct clk clk; const char *mmu; - /* Zero out the frequency, in case sizeof(ulong) != sizeof(u32) */ - info->cpu_freq = 0; - /* First try getting the frequency from the assigned clock */ ret = clk_get_by_index(dev, 0, &clk); if (!ret) { @@ -52,7 +49,7 @@ static int riscv_cpu_get_info(struct udevice *dev, struct cpu_info *info) dev_read_u32(dev, "clock-frequency", (u32 *)&info->cpu_freq); mmu = dev_read_string(dev, "mmu-type"); - if (!mmu) + if (mmu) info->features |= BIT(CPU_FEAT_MMU); return 0;