diff mbox series

[v2,4/4] riscv: cpu: check and append L1 cache to cpu features

Message ID 1590512951-1045-5-git-send-email-sagar.kadam@sifive.com
State Superseded
Delegated to: Andes
Headers show
Series update clock handler and proper cpu features | expand

Commit Message

Sagar Kadam May 26, 2020, 5:09 p.m. UTC
All cpu cores within FU540-C000 having split I/D caches.
Set the L1 feature bit using the i-cache-size as one of the
property from device tree indicating that L1 cache is present
on the cpu core.

=> cpu detail
  0: cpu@0      rv64imac
        ID = 0, freq = 999.100 MHz: L1 cache
  1: cpu@1      rv64imafdc
        ID = 1, freq = 999.100 MHz: L1 cache, MMU
  2: cpu@2      rv64imafdc
        ID = 2, freq = 999.100 MHz: L1 cache, MMU
  3: cpu@3      rv64imafdc
        ID = 3, freq = 999.100 MHz: L1 cache, MMU
  4: cpu@4      rv64imafdc
        ID = 4, freq = 999.100 MHz: L1 cache, MMU

Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
---
 drivers/cpu/riscv_cpu.c | 6 ++++++
 1 file changed, 6 insertions(+)

Comments

Pragnesh Patel May 27, 2020, 2:39 p.m. UTC | #1
Hi Sagar,

>-----Original Message-----
>From: Sagar Kadam <sagar.kadam@sifive.com>
>Sent: 26 May 2020 22:39
>To: u-boot@lists.denx.de; rick@andestech.com; lukma@denx.de
>Cc: jagan@amarulasolutions.com; bmeng.cn@gmail.com; Pragnesh Patel
><pragnesh.patel@sifive.com>; seanga2@gmail.com; Sagar Kadam
><sagar.kadam@sifive.com>
>Subject: [PATCH v2 4/4] riscv: cpu: check and append L1 cache to cpu features
>
>All cpu cores within FU540-C000 having split I/D caches.
>Set the L1 feature bit using the i-cache-size as one of the property from

s/L1 feature/L1 cache feature

>device tree indicating that L1 cache is present on the cpu core.
>
>=> cpu detail
>  0: cpu@0      rv64imac
>        ID = 0, freq = 999.100 MHz: L1 cache
>  1: cpu@1      rv64imafdc
>        ID = 1, freq = 999.100 MHz: L1 cache, MMU
>  2: cpu@2      rv64imafdc
>        ID = 2, freq = 999.100 MHz: L1 cache, MMU
>  3: cpu@3      rv64imafdc
>        ID = 3, freq = 999.100 MHz: L1 cache, MMU
>  4: cpu@4      rv64imafdc
>        ID = 4, freq = 999.100 MHz: L1 cache, MMU
>
>Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com>

Reviewed-by: Pragnesh Patel <Pragnesh.patel@sifive.com>
Sagar Kadam May 28, 2020, 8:52 a.m. UTC | #2
Hi Pragnesh,

> -----Original Message-----
> From: Pragnesh Patel <pragnesh.patel@sifive.com>
> Sent: Wednesday, May 27, 2020 8:10 PM
> To: Sagar Kadam <sagar.kadam@sifive.com>; u-boot@lists.denx.de;
> rick@andestech.com; lukma@denx.de
> Cc: jagan@amarulasolutions.com; bmeng.cn@gmail.com;
> seanga2@gmail.com
> Subject: RE: [PATCH v2 4/4] riscv: cpu: check and append L1 cache to cpu
> features
> 
> Hi Sagar,
> 
> >-----Original Message-----
> >From: Sagar Kadam <sagar.kadam@sifive.com>
> >Sent: 26 May 2020 22:39
> >To: u-boot@lists.denx.de; rick@andestech.com; lukma@denx.de
> >Cc: jagan@amarulasolutions.com; bmeng.cn@gmail.com; Pragnesh Patel
> ><pragnesh.patel@sifive.com>; seanga2@gmail.com; Sagar Kadam
> ><sagar.kadam@sifive.com>
> >Subject: [PATCH v2 4/4] riscv: cpu: check and append L1 cache to cpu
> >features
> >
> >All cpu cores within FU540-C000 having split I/D caches.
> >Set the L1 feature bit using the i-cache-size as one of the property
> >from
> 
> s/L1 feature/L1 cache feature

Ok. Will update

> 
> >device tree indicating that L1 cache is present on the cpu core.
> >
> >=> cpu detail
> >  0: cpu@0      rv64imac
> >        ID = 0, freq = 999.100 MHz: L1 cache
> >  1: cpu@1      rv64imafdc
> >        ID = 1, freq = 999.100 MHz: L1 cache, MMU
> >  2: cpu@2      rv64imafdc
> >        ID = 2, freq = 999.100 MHz: L1 cache, MMU
> >  3: cpu@3      rv64imafdc
> >        ID = 3, freq = 999.100 MHz: L1 cache, MMU
> >  4: cpu@4      rv64imafdc
> >        ID = 4, freq = 999.100 MHz: L1 cache, MMU
> >
> >Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
> 
> Reviewed-by: Pragnesh Patel <Pragnesh.patel@sifive.com>

Thanks for the review's

BR,
Sagar Kadam
diff mbox series

Patch

diff --git a/drivers/cpu/riscv_cpu.c b/drivers/cpu/riscv_cpu.c
index 8c4b5e7..ce722cb 100644
--- a/drivers/cpu/riscv_cpu.c
+++ b/drivers/cpu/riscv_cpu.c
@@ -35,6 +35,7 @@  static int riscv_cpu_get_info(struct udevice *dev, struct cpu_info *info)
 	int ret;
 	struct clk clk;
 	const char *mmu;
+	u32 split_cache_size;
 
 	/* Zero out the frequency, in case sizeof(ulong) != sizeof(u32) */
 	info->cpu_freq = 0;
@@ -57,6 +58,11 @@  static int riscv_cpu_get_info(struct udevice *dev, struct cpu_info *info)
 	if (mmu)
 		info->features |= BIT(CPU_FEAT_MMU);
 
+	/* check if I/D cache is present  */
+	ret = dev_read_u32(dev, "i-cache-size", &split_cache_size);
+	if (!ret)
+		info->features |= BIT(CPU_FEAT_L1_CACHE);
+
 	return 0;
 }