diff mbox series

[v2,2/4] riscv: dts: hifive-unleashed-a00: add cpu aliases

Message ID 1590512951-1045-3-git-send-email-sagar.kadam@sifive.com
State Superseded
Delegated to: Andes
Headers show
Series update clock handler and proper cpu features | expand

Commit Message

Sagar Kadam May 26, 2020, 5:09 p.m. UTC
Add cpu aliases to U-Boot specific dtsi for hifive-unleashed.
Without aliases we see that the CPU device sequence numbers are set
randomly and the cpu list/detail command will show it as follows:
=> cpu list
  1: cpu@0      rv64imac
  0: cpu@1      rv64imafdc
  2: cpu@2      rv64imafdc
  3: cpu@3      rv64imafdc
  4: cpu@4      rv64imafdc

Seems like CPU probing with dm-model also relies on aliases as observed
in case spi. The fu540-c000-u-boot.dtsi has cpu0/1/2/3/4 nodes and so
adding corresponding aliases we can ensure that cpu devices are assigned
proper sequence as follows:

=> cpu list
  0: cpu@0      rv64imac
  1: cpu@1      rv64imafdc
  2: cpu@2      rv64imafdc
  3: cpu@3      rv64imafdc
  4: cpu@4      rv64imafdc

Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
---
 arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

Comments

Pragnesh Patel May 29, 2020, 5:32 a.m. UTC | #1
>-----Original Message-----
>From: Sagar Kadam <sagar.kadam@sifive.com>
>Sent: 26 May 2020 22:39
>To: u-boot@lists.denx.de; rick@andestech.com; lukma@denx.de
>Cc: jagan@amarulasolutions.com; bmeng.cn@gmail.com; Pragnesh Patel
><pragnesh.patel@sifive.com>; seanga2@gmail.com; Sagar Kadam
><sagar.kadam@sifive.com>
>Subject: [PATCH v2 2/4] riscv: dts: hifive-unleashed-a00: add cpu aliases
>
>Add cpu aliases to U-Boot specific dtsi for hifive-unleashed.
>Without aliases we see that the CPU device sequence numbers are set
>randomly and the cpu list/detail command will show it as follows:
>=> cpu list
>  1: cpu@0      rv64imac
>  0: cpu@1      rv64imafdc
>  2: cpu@2      rv64imafdc
>  3: cpu@3      rv64imafdc
>  4: cpu@4      rv64imafdc
>
>Seems like CPU probing with dm-model also relies on aliases as observed in
>case spi. The fu540-c000-u-boot.dtsi has cpu0/1/2/3/4 nodes and so adding
>corresponding aliases we can ensure that cpu devices are assigned proper
>sequence as follows:
>
>=> cpu list
>  0: cpu@0      rv64imac
>  1: cpu@1      rv64imafdc
>  2: cpu@2      rv64imafdc
>  3: cpu@3      rv64imafdc
>  4: cpu@4      rv64imafdc
>
>Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
>---
> arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi | 5 +++++
> 1 file changed, 5 insertions(+)

Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
diff mbox series

Patch

diff --git a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
index 9787332..9894260 100644
--- a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
+++ b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
@@ -7,6 +7,11 @@ 
 
 / {
 	aliases {
+		cpu0 = &cpu0;
+		cpu1 = &cpu1;
+		cpu2 = &cpu2;
+		cpu3 = &cpu3;
+		cpu4 = &cpu4;
 		spi0 = &qspi0;
 		spi2 = &qspi2;
 	};