From patchwork Wed Oct 30 20:34:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Gong X-Patchwork-Id: 1186936 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.intel.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 473KfH0RPhz9sPT for ; Thu, 31 Oct 2019 07:23:34 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id AA165C21EB9; Wed, 30 Oct 2019 20:23:30 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 675FCC21E7F; Wed, 30 Oct 2019 20:21:13 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 7B0ECC21E52; Wed, 30 Oct 2019 20:20:41 +0000 (UTC) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by lists.denx.de (Postfix) with ESMTPS id 4023DC21EB9 for ; Wed, 30 Oct 2019 20:20:41 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 30 Oct 2019 13:20:40 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.68,248,1569308400"; d="scan'208";a="230582116" Received: from marshy.an.intel.com ([10.122.105.159]) by fmsmga002.fm.intel.com with ESMTP; 30 Oct 2019 13:20:40 -0700 From: richard.gong@linux.intel.com To: marex@denx.de, simon.k.r.goldschmidt@gmail.com, albert.u.boot@aribaud.net, u-boot@lists.denx.de Date: Wed, 30 Oct 2019 15:34:56 -0500 Message-Id: <1572467696-15358-5-git-send-email-richard.gong@linux.intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1572467696-15358-1-git-send-email-richard.gong@linux.intel.com> References: <1572467696-15358-1-git-send-email-richard.gong@linux.intel.com> MIME-Version: 1.0 Cc: chee.hong.ang@intel.com, radu.bacrau@intel.com, richard.gong@intel.com Subject: [U-Boot] [PATCHv2 4/4] arm: socfpga: stratix10: add environment variables for RSU support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Richard Gong Add two RSU environment variables: 1. rsu_log_level the variable is unsigned integer and its default value is RSU_DEBUG (7), which only show log with RSU_INFO,RSU_WARNING and RSU_ERR. To enable all logs (RSU_ERR, RSU_WARNING, RSU_INFO and RSU_DEBUG), you need set log level to 8 or above via “setenv rsu_log_level 8”. To disable all logs, you need set log level to 3 or below. 2. rsu_protected_slot by default there is no protected RSU slot, you need run "setenv rsu_protected_slot ” to set a slot protected, and “setenv rsu_protected_slot ” to unset a protected slot. Signed-off-by: Richard Gong --- arch/arm/mach-socfpga/misc_s10.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/mach-socfpga/misc_s10.c b/arch/arm/mach-socfpga/misc_s10.c index 0a5fab1..c9a6f00 100644 --- a/arch/arm/mach-socfpga/misc_s10.c +++ b/arch/arm/mach-socfpga/misc_s10.c @@ -21,6 +21,8 @@ #include +#define RSU_DEFAULT_LOG_LEVEL 7 + DECLARE_GLOBAL_DATA_PTR; static struct socfpga_system_manager *sysmgr_regs = @@ -136,10 +138,17 @@ int print_cpuinfo(void) int arch_misc_init(void) { char qspi_string[13]; + char level[4]; + + snprintf(level, sizeof(level), "%u", RSU_DEFAULT_LOG_LEVEL); sprintf(qspi_string, "<0x%08x>", cm_get_qspi_controller_clk_hz()); env_set("qspi_clock", qspi_string); + /* setup for RSU */ + env_set("rsu_protected_slot", ""); + env_set("rsu_log_level", level); + socfpga_set_phymode(); return 0; }