From patchwork Wed Oct 30 13:38:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabien DESSENNE X-Patchwork-Id: 1186714 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=st.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=st.com header.i=@st.com header.b="KjhSEsY3"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 4738k24mV6z9sPL for ; Thu, 31 Oct 2019 00:41:14 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 65C30C21DD3; Wed, 30 Oct 2019 13:39:40 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id D0ED2C21E18; Wed, 30 Oct 2019 13:38:56 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id E0B7EC21D56; Wed, 30 Oct 2019 13:38:49 +0000 (UTC) Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [62.209.51.94]) by lists.denx.de (Postfix) with ESMTPS id B4970C21C51 for ; Wed, 30 Oct 2019 13:38:49 +0000 (UTC) Received: from pps.filterd (m0046037.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x9UDboMj008191; Wed, 30 Oct 2019 14:38:49 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=st.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=STMicroelectronics; bh=SW1xPiVZH1A4Yf2FcG6NbkJ9XTCdZ5jNUUP8oK8vKwE=; b=KjhSEsY3cLCCt40+cdRUyGzBO2skCgszzNSmj6kcIu0OHqJuU6DSJCByNHLHtSathVU4 MSxvAqMfsEMtiZdkStokai5YFDsAE7rxmQmgSGGqYXxFO8ILIvqNxzxbE/lvL3MAqeBa Ry+TcsSgXTiBc7lX2oQSJ/+Mxi5YeTHimMQL/fXy7MeinhwN5Wxn2A6QcnlMEhuo6MxN Euzwy/Kvp32ssJGn1Ju5+GeI2scK7r+afhy1wcExjxOD+iKFpYD90TnuEKQ1rXxjoOat jKqYVK8wWYU4yhYQ1L9E7Tkj5YPDKfv0gdx+UFKOceR7lcYy+GPxpnwugDvdA5hv0u98 mg== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 2vxwhe3xuq-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 30 Oct 2019 14:38:49 +0100 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id ABB39100039; Wed, 30 Oct 2019 14:38:47 +0100 (CET) Received: from Webmail-eu.st.com (Safex1hubcas22.st.com [10.75.90.92]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id A1E542BEC75; Wed, 30 Oct 2019 14:38:47 +0100 (CET) Received: from SAFEX1HUBCAS24.st.com (10.75.90.95) by Safex1hubcas22.st.com (10.75.90.92) with Microsoft SMTP Server (TLS) id 14.3.439.0; Wed, 30 Oct 2019 14:38:47 +0100 Received: from localhost (10.201.23.25) by webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.439.0; Wed, 30 Oct 2019 14:38:47 +0100 From: Fabien Dessenne To: Simon Glass , Patrick Delaunay , Patrice Chotard , "Lokesh Vutla" , Suman Anna Date: Wed, 30 Oct 2019 14:38:30 +0100 Message-ID: <1572442713-26353-4-git-send-email-fabien.dessenne@st.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1572442713-26353-1-git-send-email-fabien.dessenne@st.com> References: <1572442713-26353-1-git-send-email-fabien.dessenne@st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.23.25] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.95,1.0.8 definitions=2019-10-30_06:2019-10-30,2019-10-30 signatures=0 Cc: uboot-stm32@st-md-mailman.stormreply.com, u-boot@lists.denx.de, Arnaud Pouliquen , Loic Pallardy , Fabien Dessenne Subject: [U-Boot] [PATCH v2 3/6] stm32mp1: reset coprocessor status at cold boot X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Reset ResourceTableAddress and CoprocessorState at cold boot, preserve these values at standby wakeup. Signed-off-by: Fabien Dessenne Acked-by: Patrick Delaunay --- arch/arm/mach-stm32mp/cpu.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/mach-stm32mp/cpu.c b/arch/arm/mach-stm32mp/cpu.c index a46e843..e24abf5 100644 --- a/arch/arm/mach-stm32mp/cpu.c +++ b/arch/arm/mach-stm32mp/cpu.c @@ -34,7 +34,9 @@ #define TAMP_CR1 (STM32_TAMP_BASE + 0x00) #define PWR_CR1 (STM32_PWR_BASE + 0x00) +#define PWR_MCUCR (STM32_PWR_BASE + 0x14) #define PWR_CR1_DBP BIT(8) +#define PWR_MCUCR_SBF BIT(6) /* DBGMCU register */ #define DBGMCU_IDC (STM32_DBGMCU_BASE + 0x00) @@ -205,6 +207,11 @@ int arch_cpu_init(void) security_init(); update_bootmode(); #endif + /* Reset Coprocessor state unless it wakes up from Standby power mode */ + if (!(readl(PWR_MCUCR) & PWR_MCUCR_SBF)) { + writel(TAMP_COPRO_STATE_OFF, TAMP_COPRO_STATE); + writel(0, TAMP_COPRO_RSC_TBL_ADDRESS); + } #endif boot_mode = get_bootmode();