From patchwork Mon Oct 7 13:29:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Yannick FERTRE X-Patchwork-Id: 1172777 X-Patchwork-Delegate: agust@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=st.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=st.com header.i=@st.com header.b="ovgpgEeu"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 46n1gH1t3Lz9s4Y for ; Tue, 8 Oct 2019 00:34:51 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id CB9A3C21F13; Mon, 7 Oct 2019 13:33:34 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=KHOP_BIG_TO_CC, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id DF19FC21F51; Mon, 7 Oct 2019 13:30:40 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id DBF85C21F4A; Mon, 7 Oct 2019 13:29:48 +0000 (UTC) Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) by lists.denx.de (Postfix) with ESMTPS id 1941DC21F35 for ; Mon, 7 Oct 2019 13:29:46 +0000 (UTC) Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx08-00178001.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x97DLCEe028595; Mon, 7 Oct 2019 15:29:44 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=st.com; h=from : to : subject : date : message-id : in-reply-to : references : mime-version : content-type : content-transfer-encoding; s=STMicroelectronics; bh=gA1aY/jgi1FDZM6Wnld+XjiRYJmKCacWDKOeTVLTq7Y=; b=ovgpgEeu67qAHbcASH8tqKXuDxiAfh51EovSETtSoNU995o6eUlmlJflr4qOmlksXsnw 7fZRrdGDf0gA4omdCy7w+bfSvSdEjSDbAgKEoOphkjBk4MBDAKFZVG+20rWmvsT8D9wF ZlOu6GiNgOfdk81oa/20BLLxTW8dALgUGtxzMschVl+QXrBOEDyDMgt5A/p+DxmM2qke hrQBMdihLBAy+h+PBN7uxjTbBtED5lRRRKJ7x20aXjDRUF8/m/NWO9T+mUHPWUjNtUOL Gyy62wxzBw1GgEve6Cmf0Fx17x3k32P53J+bXUjnPiYghhQLSEQMTLuErBAJj46L4731 xg== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-00178001.pphosted.com with ESMTP id 2vegagtxr0-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 07 Oct 2019 15:29:44 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 5EF0B100038; Mon, 7 Oct 2019 15:29:43 +0200 (CEST) Received: from Webmail-eu.st.com (Safex1hubcas21.st.com [10.75.90.44]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 537D92BFE0F; Mon, 7 Oct 2019 15:29:43 +0200 (CEST) Received: from SAFEX1HUBCAS22.st.com (10.75.90.93) by SAFEX1HUBCAS21.st.com (10.75.90.44) with Microsoft SMTP Server (TLS) id 14.3.439.0; Mon, 7 Oct 2019 15:29:43 +0200 Received: from localhost (10.201.23.97) by Webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.439.0; Mon, 7 Oct 2019 15:29:42 +0200 From: =?utf-8?q?Yannick_Fertr=C3=A9?= To: Vikas Manocha , Benjamin Gaignard , Albert Aribaud , Patrick Delaunay , Simon Glass , Anatolij Gustschin , Patrice Chotard , Yannick Fertre , Philippe Cornu , Jens Wiklander , "Eugen Hristev" , Heinrich Schuchardt , Simon Goldschmidt , , Date: Mon, 7 Oct 2019 15:29:11 +0200 Message-ID: <1570454955-21298-12-git-send-email-yannick.fertre@st.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1570454955-21298-1-git-send-email-yannick.fertre@st.com> References: <1570454955-21298-1-git-send-email-yannick.fertre@st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.23.97] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.95,1.0.8 definitions=2019-10-07_02:2019-10-07,2019-10-07 signatures=0 Subject: [U-Boot] [PATCH v5 11/15] ARM: dts: stm32f769: add display for STM32F769 disco board X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Enable the display controller, mipi dsi bridge & panel. Set panel display timings. Signed-off-by: Yannick Fertré --- arch/arm/dts/stm32f769-disco-u-boot.dtsi | 62 ++++++++++++++++++++++++++++++++ 1 file changed, 62 insertions(+) diff --git a/arch/arm/dts/stm32f769-disco-u-boot.dtsi b/arch/arm/dts/stm32f769-disco-u-boot.dtsi index 209a82c..c1d7d6b 100644 --- a/arch/arm/dts/stm32f769-disco-u-boot.dtsi +++ b/arch/arm/dts/stm32f769-disco-u-boot.dtsi @@ -28,10 +28,72 @@ button-gpio = <&gpioa 0 0>; }; + dsi_host: dsi_host { + compatible = "synopsys,dw-mipi-dsi"; + status = "okay"; + }; + led1 { compatible = "st,led1"; led-gpio = <&gpioj 5 0>; }; + + panel: panel { + compatible = "orisetech,otm8009a"; + reset-gpios = <&gpioj 15 1>; + status = "okay"; + + port { + panel_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + }; + + soc { + dsi: dsi@40016c00 { + compatible = "st,stm32-dsi"; + reg = <0x40016C00 0x800>; + resets = <&rcc STM32F7_APB2_RESET(DSI)>; + clocks = <&rcc 0 STM32F7_APB2_CLOCK(DSI)>, + <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>, + <&clk_hse>; + clock-names = "pclk", "px_clk", "ref"; + u-boot,dm-pre-reloc; + status = "okay"; + + ports { + port@0 { + dsi_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + port@1 { + dsi_in: endpoint { + remote-endpoint = <&dp_out>; + }; + }; + }; + }; + + ltdc: display-controller@40016800 { + compatible = "st,stm32-ltdc"; + reg = <0x40016800 0x200>; + resets = <&rcc STM32F7_APB2_RESET(LTDC)>; + clocks = <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>; + + status = "okay"; + u-boot,dm-pre-reloc; + + ports { + port@0 { + dp_out: endpoint { + remote-endpoint = <&dsi_in>; + }; + }; + }; + }; + }; }; &fmc {