From patchwork Wed Sep 18 02:15:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?V2VpamllIEdhbyAo6auY5oOf5p2wKQ==?= X-Patchwork-Id: 1163673 X-Patchwork-Delegate: daniel.schwierzeck@googlemail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 46Y3cv5hQhz9sN1 for ; Wed, 18 Sep 2019 12:21:19 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 7BCE5C21E36; Wed, 18 Sep 2019 02:18:33 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: * X-Spam-Status: No, score=1.3 required=5.0 tests=RDNS_NONE, UNPARSEABLE_RELAY autolearn=no autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id C3A3BC21E44; Wed, 18 Sep 2019 02:16:51 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 7E8A1C21ECF; Wed, 18 Sep 2019 02:16:32 +0000 (UTC) Received: from mailgw02.mediatek.com (unknown [1.203.163.81]) by lists.denx.de (Postfix) with ESMTP id 75460C21E56 for ; Wed, 18 Sep 2019 02:16:29 +0000 (UTC) X-UUID: dcd3ff0a1fd240098b212c7ed414c31b-20190918 X-UUID: dcd3ff0a1fd240098b212c7ed414c31b-20190918 Received: from mtkcas36.mediatek.inc [(172.27.4.253)] by mailgw02.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLS) with ESMTP id 1758554753; Wed, 18 Sep 2019 10:16:24 +0800 Received: from MTKCAS32.mediatek.inc (172.27.4.184) by MTKMBS31N2.mediatek.inc (172.27.4.87) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 18 Sep 2019 10:16:24 +0800 Received: from mcddlt001.mediatek.inc (172.27.4.253) by MTKCAS32.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Wed, 18 Sep 2019 10:16:23 +0800 From: Weijie Gao To: Date: Wed, 18 Sep 2019 10:15:41 +0800 Message-ID: <1568772962-18697-8-git-send-email-weijie.gao@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1568772962-18697-1-git-send-email-weijie.gao@mediatek.com> References: <1568772962-18697-1-git-send-email-weijie.gao@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 9C824DB2C1875DB9DFE1A2BBC5FF895423A07C682B9F15A29E4B189586FE2E9F2000:8 X-MTK: N Cc: Tom Rini , Stefan Roese , Joe Hershberger , Stefan Roese , GSS_MTK_Uboot_upstream Subject: [U-Boot] [PATCH v2 07/28] spi: mt7621-spi: use clock frequency from clk driver X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This patch lets the spi driver to use clock provided by the clk driver since the new clk-mt7628 driver provides accurate sys clock frequency. Signed-off-by: Weijie Gao --- v2: newly added --- drivers/spi/mt7621_spi.c | 20 +++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/drivers/spi/mt7621_spi.c b/drivers/spi/mt7621_spi.c index 107e58f657..b37f859b98 100644 --- a/drivers/spi/mt7621_spi.c +++ b/drivers/spi/mt7621_spi.c @@ -9,6 +9,7 @@ */ #include +#include #include #include #include @@ -266,19 +267,24 @@ static int mt7621_spi_xfer(struct udevice *dev, unsigned int bitlen, static int mt7621_spi_probe(struct udevice *dev) { struct mt7621_spi *rs = dev_get_priv(dev); + struct clk clk; + int ret; rs->base = dev_remap_addr(dev); if (!rs->base) return -EINVAL; - /* - * Read input clock via DT for now. At some point this should be - * replaced by implementing a clock driver for this SoC and getting - * the SPI frequency via this clock driver. - */ - rs->sys_freq = dev_read_u32_default(dev, "clock-frequency", 0); + ret = clk_get_by_index(dev, 0, &clk); + if (ret < 0) { + printf("Please provide a clock!\n"); + return ret; + } + + clk_enable(&clk); + + rs->sys_freq = clk_get_rate(&clk); if (!rs->sys_freq) { - printf("Please provide clock-frequency!\n"); + printf("Please provide a valid clock!\n"); return -EINVAL; }