diff mbox series

[U-Boot,v2,01/28] serial: serial_mtk: enable FIFO and disable flow control

Message ID 1568772962-18697-2-git-send-email-weijie.gao@mediatek.com
State Superseded
Delegated to: Daniel Schwierzeck
Headers show
Series Add and update drivers for MediaTek MT76x8 SoCs | expand

Commit Message

Weijie Gao (高惟杰) Sept. 18, 2019, 2:15 a.m. UTC 
This patch adds codes to enable FIFO and disable flow control taken from
ns16550 driver.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
 drivers/serial/serial_mtk.c | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)
diff mbox series

Patch

diff --git a/drivers/serial/serial_mtk.c b/drivers/serial/serial_mtk.c
index bce1be8227..11892a8740 100644
--- a/drivers/serial/serial_mtk.c
+++ b/drivers/serial/serial_mtk.c
@@ -46,6 +46,22 @@  struct mtk_serial_regs {
 
 #define UART_LSR_DR	0x01		/* Data ready */
 #define UART_LSR_THRE	0x20		/* Xmit holding register empty */
+#define UART_LSR_TEMT	0x40		/* Xmitter empty */
+
+#define UART_MCR_DTR	0x01		/* DTR   */
+#define UART_MCR_RTS	0x02		/* RTS   */
+
+#define UART_FCR_FIFO_EN	0x01	/* Fifo enable */
+#define UART_FCR_RXSR		0x02	/* Receiver soft reset */
+#define UART_FCR_TXSR		0x04	/* Transmitter soft reset */
+
+#define UART_MCRVAL (UART_MCR_DTR | \
+		     UART_MCR_RTS)
+
+/* Clear & enable FIFOs */
+#define UART_FCRVAL (UART_FCR_FIFO_EN | \
+		     UART_FCR_RXSR |	\
+		     UART_FCR_TXSR)
 
 /* the data is correct if the real baud is within 3%. */
 #define BAUD_ALLOW_MAX(baud)	((baud) + (baud) * 3 / 100)
@@ -175,6 +191,9 @@  static int mtk_serial_probe(struct udevice *dev)
 	/* Disable interrupt */
 	writel(0, &priv->regs->ier);
 
+	writel(UART_MCRVAL, &priv->regs->mcr);
+	writel(UART_FCRVAL, &priv->regs->fcr);
+
 	return 0;
 }
 
@@ -248,6 +267,8 @@  static inline void _debug_uart_init(void)
 	priv.clock = CONFIG_DEBUG_UART_CLOCK;
 
 	writel(0, &priv.regs->ier);
+	writel(UART_MCRVAL, &priv.regs->mcr);
+	writel(UART_FCRVAL, &priv.regs->fcr);
 
 	_mtk_serial_setbrg(&priv, CONFIG_BAUDRATE);
 }