From patchwork Wed Aug 28 06:38:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?V2VpamllIEdhbyAo6auY5oOf5p2wKQ==?= X-Patchwork-Id: 1154214 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 46JGTc57M1z9sN6 for ; Wed, 28 Aug 2019 16:45:40 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 6318BC21F27; Wed, 28 Aug 2019 06:41:58 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: * X-Spam-Status: No, score=1.3 required=5.0 tests=RDNS_NONE, UNPARSEABLE_RELAY autolearn=no autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 64E78C21F27; Wed, 28 Aug 2019 06:39:54 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 68DF6C21F47; Wed, 28 Aug 2019 06:39:21 +0000 (UTC) Received: from mailgw02.mediatek.com (unknown [1.203.163.81]) by lists.denx.de (Postfix) with ESMTP id 63973C21EFD for ; Wed, 28 Aug 2019 06:39:17 +0000 (UTC) X-UUID: 59851e9f062d43a68deec9febf5280ec-20190828 X-UUID: 59851e9f062d43a68deec9febf5280ec-20190828 Received: from mtkcas35.mediatek.inc [(172.27.4.253)] by mailgw02.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLS) with ESMTP id 699324844; Wed, 28 Aug 2019 14:39:18 +0800 Received: from MTKCAS36.mediatek.inc (172.27.4.186) by MTKMBS31N1.mediatek.inc (172.27.4.69) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 28 Aug 2019 14:39:16 +0800 Received: from mcddlt001.mediatek.inc (172.27.4.253) by MTKCAS36.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Wed, 28 Aug 2019 14:39:16 +0800 From: Weijie Gao To: Date: Wed, 28 Aug 2019 14:38:00 +0800 Message-ID: <1566974291-11750-16-git-send-email-weijie.gao@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1566974291-11750-1-git-send-email-weijie.gao@mediatek.com> References: <1566974291-11750-1-git-send-email-weijie.gao@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 8DADC141CE5E02B6F2FE358CA633C5CFEC7E47F2C9102277B1D65B2043044A3F2000:8 X-MTK: N Cc: Tom Rini , Joe Hershberger , Stefan Roese , GSS_MTK_Uboot_upstream Subject: [U-Boot] [PATCH 15/26] net: mt7628-eth: remove hardcoded gpio settings and regmap-based phy reset X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This patch removes hardcoded gpio settings as they have been replaced by pinctrl in dts, and also replaces regmap-based phy reset with a more generic reset controller. Signed-off-by: Weijie Gao Reviewed-by: Stefan Roese --- drivers/net/mt7628-eth.c | 45 +++++++--------------------------------- 1 file changed, 8 insertions(+), 37 deletions(-) diff --git a/drivers/net/mt7628-eth.c b/drivers/net/mt7628-eth.c index 7833b2f47a..4675b0f003 100644 --- a/drivers/net/mt7628-eth.c +++ b/drivers/net/mt7628-eth.c @@ -18,23 +18,12 @@ #include #include #include -#include -#include +#include #include #include #include #include -/* System controller register */ -#define MT7628_RSTCTRL_REG 0x34 -#define RSTCTRL_EPHY_RST BIT(24) - -#define MT7628_AGPIO_CFG_REG 0x3c -#define MT7628_EPHY_GPIO_AIO_EN GENMASK(20, 17) -#define MT7628_EPHY_P0_DIS BIT(16) - -#define MT7628_GPIO2_MODE_REG 0x64 - /* Ethernet frame engine register */ #define PDMA_RELATED 0x0800 @@ -137,7 +126,6 @@ struct fe_tx_dma { struct mt7628_eth_dev { void __iomem *base; /* frame engine base address */ void __iomem *eth_sw_base; /* switch base address */ - struct regmap *sysctrl_regmap; /* system-controller reg-map */ struct mii_dev *bus; @@ -150,6 +138,8 @@ struct mt7628_eth_dev { int rx_dma_idx; /* Point to the next TXD in TXD Ring0 CPU wants to use */ int tx_dma_idx; + + struct reset_ctl rst_ephy; }; static int mdio_wait_read(struct mt7628_eth_dev *priv, u32 mask, bool mask_set) @@ -301,20 +291,9 @@ static void rt305x_esw_init(struct mt7628_eth_dev *priv) /* 1us cycle number=125 (FE's clock=125Mhz) */ writel(0x7d000000, base + MT7628_SWITCH_BMU_CTRL); - /* Configure analog GPIO setup */ - regmap_update_bits(priv->sysctrl_regmap, MT7628_AGPIO_CFG_REG, - MT7628_EPHY_P0_DIS, MT7628_EPHY_GPIO_AIO_EN); - /* Reset PHY */ - regmap_update_bits(priv->sysctrl_regmap, MT7628_RSTCTRL_REG, - 0, RSTCTRL_EPHY_RST); - regmap_update_bits(priv->sysctrl_regmap, MT7628_RSTCTRL_REG, - RSTCTRL_EPHY_RST, 0); - mdelay(10); - - /* Set P0 EPHY LED mode */ - regmap_update_bits(priv->sysctrl_regmap, MT7628_GPIO2_MODE_REG, - 0x0ffc0ffc, 0x05540554); + reset_assert(&priv->rst_ephy); + reset_deassert(&priv->rst_ephy); mdelay(10); mt7628_ephy_init(priv); @@ -558,7 +537,6 @@ static void mt7628_eth_stop(struct udevice *dev) static int mt7628_eth_probe(struct udevice *dev) { struct mt7628_eth_dev *priv = dev_get_priv(dev); - struct udevice *syscon; struct mii_dev *bus; int ret; int i; @@ -573,20 +551,13 @@ static int mt7628_eth_probe(struct udevice *dev) if (IS_ERR(priv->eth_sw_base)) return PTR_ERR(priv->eth_sw_base); - /* Get system controller regmap */ - ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, - "syscon", &syscon); + /* Reset controller */ + ret = reset_get_by_name(dev, "ephy", &priv->rst_ephy); if (ret) { - pr_err("unable to find syscon device\n"); + pr_err("unable to find reset controller for ethernet PHYs\n"); return ret; } - priv->sysctrl_regmap = syscon_get_regmap(syscon); - if (!priv->sysctrl_regmap) { - pr_err("unable to find regmap\n"); - return -ENODEV; - } - /* Put rx and tx rings into KSEG1 area (uncached) */ priv->tx_ring = (struct fe_tx_dma *) KSEG1ADDR(memalign(ARCH_DMA_MINALIGN,