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[U-Boot,v5] board/BuR/zynq/brsmarc2: initial commit

Message ID 1563366318-6136-1-git-send-email-hannes.schmelzer@br-automation.com
State Deferred
Delegated to: Michal Simek
Headers show
Series [U-Boot,v5] board/BuR/zynq/brsmarc2: initial commit | expand

Commit Message

Hannes Schmelzer July 17, 2019, 12:25 p.m. UTC 
This commit adds the first of a few more Xilinx ZYNQ based SoM boards.

The SoM is based on Xilinx Zynq 7000 SoC.
Mainly vxWorks 6.9.4.x is running on the board,
doing some PLC stuff on various carrier boards.

Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>

---

Changes in v5:
- rebase to current master
- dts: fix dtc compiler warnings regarding cell-size in board-thermal
- remove brsmarc2_r512 target (can be covered all with brsmarc2)

Changes in v4:
- use CONFIG_SYS_AUTOLOAD instead defining it in environment
- drop duplicate CONFIG_BOOTP_MAY_FAIL
- drop duplicate CONFIG_ENV_OVERWRITE
- move CONFIG_MII from boardheader to Kconfig
- dts: change temperature-sensor node names to fit dts spec
- dts: change rtc node name to fit dts spec
- dts: drop memory node from -common-dtsi
- dts: move vxWorks (bur) specific bindings at phys to -vxworks.dtsi
- dts: minor cosmetic (whitespace) cleanup
- dts: move resetcontroller node to -vxworks.dtsi

Changes in v3:
- drop silicon version 1/2 from ps7_init_gpl.c (they are obsolete)
- board.c: drop obsolete board_eth_init(...)
- board.c: strip down dram_init(..)
- board.c: drop unused #include
- board.c: cleanup comments
- move CONFIG_ZYNQ_SERIAL from boardheader to Kconfig
- move CONFIG_FPGA_ZYNQPL from boardheader to Kconfig
- fix comments in boardheader
- drop *_SYS_LDSCRIPT from boardheader (defined in Kconfig)
- drop CONFIG_SYS_MALLOC_LEN (defined in Kconfig)
- dop CONFIG_ENV_SPI_MAX_HZ from boardheader (defined in Kconfig)
- dts: split vxWorks specific parts away from dts into separate file
- dts: add compatible string to factory-settings node
- dts: drop invalid (zero)= mac-addresses on gem0/gem1
- dts: fixup style on ethernet_phy1 description
- dts: add comments to phy's
- drop helper-scripts for taking vivado handoff files into tree

Changes in v2:
- fix SDPX tag in Make-files/rules

 arch/arm/dts/Makefile                   |   1 +
 arch/arm/dts/zynq-brsmarc2-common.dtsi  | 157 ++++++++++++++++++
 arch/arm/dts/zynq-brsmarc2-vxworks.dtsi | 143 +++++++++++++++++
 arch/arm/dts/zynq-brsmarc2.dts          |   8 +
 board/BuR/zynq/.gitignore               |   1 +
 board/BuR/zynq/MAINTAINERS              |   6 +
 board/BuR/zynq/Makefile                 |  16 ++
 board/BuR/zynq/brsmarc2/board.c         |  63 ++++++++
 board/BuR/zynq/brsmarc2/ps7_init_gpl.c  | 276 ++++++++++++++++++++++++++++++++
 board/BuR/zynq/config.mk                |  49 ++++++
 configs/brsmarc2_defconfig              |  75 +++++++++
 include/configs/brsmarc2.h              | 150 +++++++++++++++++
 12 files changed, 945 insertions(+)
 create mode 100644 arch/arm/dts/zynq-brsmarc2-common.dtsi
 create mode 100644 arch/arm/dts/zynq-brsmarc2-vxworks.dtsi
 create mode 100644 arch/arm/dts/zynq-brsmarc2.dts
 create mode 100644 board/BuR/zynq/.gitignore
 create mode 100644 board/BuR/zynq/MAINTAINERS
 create mode 100644 board/BuR/zynq/Makefile
 create mode 100644 board/BuR/zynq/brsmarc2/board.c
 create mode 100644 board/BuR/zynq/brsmarc2/ps7_init_gpl.c
 create mode 100644 board/BuR/zynq/config.mk
 create mode 100644 configs/brsmarc2_defconfig
 create mode 100644 include/configs/brsmarc2.h

Comments

Michal Simek Aug. 14, 2019, 6:10 a.m. UTC | #1 
Hi,

first of all sorry for delay I had vacation.

On 17. 07. 19 14:25, Hannes Schmelzer wrote:
> This commit adds the first of a few more Xilinx ZYNQ based SoM boards.
> 
> The SoM is based on Xilinx Zynq 7000 SoC.
> Mainly vxWorks 6.9.4.x is running on the board,
> doing some PLC stuff on various carrier boards.
> 
> Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
> 
> ---
> 
> Changes in v5:
> - rebase to current master
> - dts: fix dtc compiler warnings regarding cell-size in board-thermal
> - remove brsmarc2_r512 target (can be covered all with brsmarc2)
> 
> Changes in v4:
> - use CONFIG_SYS_AUTOLOAD instead defining it in environment
> - drop duplicate CONFIG_BOOTP_MAY_FAIL
> - drop duplicate CONFIG_ENV_OVERWRITE
> - move CONFIG_MII from boardheader to Kconfig
> - dts: change temperature-sensor node names to fit dts spec
> - dts: change rtc node name to fit dts spec
> - dts: drop memory node from -common-dtsi
> - dts: move vxWorks (bur) specific bindings at phys to -vxworks.dtsi
> - dts: minor cosmetic (whitespace) cleanup
> - dts: move resetcontroller node to -vxworks.dtsi
> 
> Changes in v3:
> - drop silicon version 1/2 from ps7_init_gpl.c (they are obsolete)
> - board.c: drop obsolete board_eth_init(...)
> - board.c: strip down dram_init(..)
> - board.c: drop unused #include
> - board.c: cleanup comments
> - move CONFIG_ZYNQ_SERIAL from boardheader to Kconfig
> - move CONFIG_FPGA_ZYNQPL from boardheader to Kconfig
> - fix comments in boardheader
> - drop *_SYS_LDSCRIPT from boardheader (defined in Kconfig)
> - drop CONFIG_SYS_MALLOC_LEN (defined in Kconfig)
> - dop CONFIG_ENV_SPI_MAX_HZ from boardheader (defined in Kconfig)
> - dts: split vxWorks specific parts away from dts into separate file
> - dts: add compatible string to factory-settings node
> - dts: drop invalid (zero)= mac-addresses on gem0/gem1
> - dts: fixup style on ethernet_phy1 description
> - dts: add comments to phy's
> - drop helper-scripts for taking vivado handoff files into tree
> 
> Changes in v2:
> - fix SDPX tag in Make-files/rules
> 
>  arch/arm/dts/Makefile                   |   1 +
>  arch/arm/dts/zynq-brsmarc2-common.dtsi  | 157 ++++++++++++++++++
>  arch/arm/dts/zynq-brsmarc2-vxworks.dtsi | 143 +++++++++++++++++
>  arch/arm/dts/zynq-brsmarc2.dts          |   8 +
>  board/BuR/zynq/.gitignore               |   1 +
>  board/BuR/zynq/MAINTAINERS              |   6 +
>  board/BuR/zynq/Makefile                 |  16 ++
>  board/BuR/zynq/brsmarc2/board.c         |  63 ++++++++
>  board/BuR/zynq/brsmarc2/ps7_init_gpl.c  | 276 ++++++++++++++++++++++++++++++++
>  board/BuR/zynq/config.mk                |  49 ++++++
>  configs/brsmarc2_defconfig              |  75 +++++++++
>  include/configs/brsmarc2.h              | 150 +++++++++++++++++
>  12 files changed, 945 insertions(+)
>  create mode 100644 arch/arm/dts/zynq-brsmarc2-common.dtsi
>  create mode 100644 arch/arm/dts/zynq-brsmarc2-vxworks.dtsi
>  create mode 100644 arch/arm/dts/zynq-brsmarc2.dts
>  create mode 100644 board/BuR/zynq/.gitignore
>  create mode 100644 board/BuR/zynq/MAINTAINERS
>  create mode 100644 board/BuR/zynq/Makefile
>  create mode 100644 board/BuR/zynq/brsmarc2/board.c
>  create mode 100644 board/BuR/zynq/brsmarc2/ps7_init_gpl.c
>  create mode 100644 board/BuR/zynq/config.mk
>  create mode 100644 configs/brsmarc2_defconfig
>  create mode 100644 include/configs/brsmarc2.h
> 
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 20dbc2f..e718fe6 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -233,6 +233,7 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \
>  	zynq-zc770-xm011-x16.dtb \
>  	zynq-zc770-xm012.dtb \
>  	zynq-zc770-xm013.dtb \
> +	zynq-brsmarc2.dtb \
>  	zynq-zed.dtb \
>  	zynq-zturn.dtb \
>  	zynq-zybo.dtb \
> diff --git a/arch/arm/dts/zynq-brsmarc2-common.dtsi b/arch/arm/dts/zynq-brsmarc2-common.dtsi
> new file mode 100644
> index 0000000..09b88c7
> --- /dev/null
> +++ b/arch/arm/dts/zynq-brsmarc2-common.dtsi
> @@ -0,0 +1,157 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * common DTS part for B&R BRSMARC2 boards
> + *
> + * Copyright (C) 2019 B&R Industrial Automation GmbH
> + */
> +
> +/dts-v1/;
> +#include "zynq-7000.dtsi"
> +#include <dt-bindings/thermal/thermal.h>
> +#include <dt-bindings/gpio/gpio.h>
> +
> +/ {
> +	model = "BRSMARC2 Zynq SoM";
> +	compatible = "xlnx,zynq-7000";
> +
> +	aliases {
> +		ethernet0 = &gem0;
> +		ethernet1 = &gem1;
> +		i2c0 = &i2c0;
> +		serial0 = &uart0;
> +		spi0 = &qspi;
> +		mmc0 = &sdhci0;
> +		can0 = &can0;
> +		can1 = &can1;
> +	};
> +
> +	memory {
> +		device_type = "memory";
> +		reg = <0x0 0x20000000>;
> +	};
> +
> +	chosen {
> +		bootargs = "console=ttyPS0,115200 earlyprintk";

This looks like as Linux command line. If yes you should use earlycon
instead of earlyprintk which is used for debugging.


> +		stdout-path = "serial0:115200n8";
> +	};
> +
> +	usb_phy0: phy0 {
> +		compatible = "usb-nop-xceiv";
> +		#phy-cells = <0>;
> +	};
> +
> +	board_thermal: board-thermal {
> +		polling-delay-passive = <1000>; /* milliseconds */
> +		polling-delay = <2500>; /* milliseconds */
> +
> +		thermal-sensors = <&temp_core 0>;
> +
> +		trips {
> +			crit_trip: crit-trip {
> +				temperature = <100000>; /* millicelsius */
> +				hysteresis = <5000>; /* millicelsius */
> +				type = "critical";
> +			};
> +		};
> +		cooling-maps {
> +			map0 {
> +				trip = <&crit_trip>;
> +				cooling-device =
> +				<&resetc THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> +			};
> +		};
> +	};
> +};
> +
> +&amba {
> +	ocm: sram@fffc0000 {
> +		compatible = "mmio-sram";
> +		reg = <0xfffc0000 0x10000>;
> +	};
> +};
> +
> +&clkc {
> +	ps-clk-frequency = <33333333>;
> +};
> +
> +&gem0 {
> +	status = "okay";
> +	phy-mode = "rgmii-id";
> +	phy-handle = <&ethernet_phy0>;
> +
> +	/* DP83822 phy */
> +	ethernet_phy0: ethernet-phy@1 {
> +		reg = <1>;
> +	};
> +};
> +
> +&gem1 {
> +	status = "okay";
> +	phy-mode = "rgmii-id";
> +	phy-handle = <&ethernet_phy1>;
> +
> +	/* DP83822 phy */
> +	ethernet_phy1: ethernet-phy@3 {
> +		reg = <3>;
> +	};
> +};
> +
> +&i2c0 {
> +	u-boot,dm-pre-reloc;
> +	status = "okay";
> +	clock-frequency = <100000>;
> +
> +	boardtemp: temperature-sensor@49 {
> +		#thermal-sensor-cells = <0>;
> +		compatible = "nxp,pct2075";
> +		reg = <0x49>;
> +	};
> +
> +	temp_core: temperature-sensor@4c { /* temp. zynq die */
> +		#thermal-sensor-cells = <1>;
> +		compatible = "ti,tmp431";
> +		reg = <0x4c>;
> +	};
> +
> +	extrtc: rtc@51 {	/* realtime clock */
> +		compatible = "epson,rx8571";
> +		reg = <0x51>;
> +	};
> +};
> +
> +&qspi {
> +	u-boot,dm-pre-reloc;
> +	status = "okay";
> +	spi-max-frequency = <100000000>;
> +	spi_flash: spiflash@0 {
> +		u-boot,dm-pre-reloc;
> +		compatible = "spidev", "spi-flash";
> +		spi-max-frequency = <100000000>;
> +		reg = <0>;
> +	};
> +};
> +
> +&i2c1 {
> +	status = "okay";
> +	clock-frequency = <100000>;
> +};
> +
> +&sdhci0 {
> +	status = "okay";
> +	max-frequency = <25000000>;
> +};
> +
> +&uart0 {
> +	u-boot,dm-pre-reloc;
> +	status = "okay";
> +};
> +
> +&usb0 {
> +	status = "okay";
> +	dr_mode = "host";
> +	usb-phy = <&usb_phy0>;
> +};
> +
> +&gpio0 {
> +	u-boot,dm-pre-reloc;
> +};
> diff --git a/arch/arm/dts/zynq-brsmarc2-vxworks.dtsi b/arch/arm/dts/zynq-brsmarc2-vxworks.dtsi
> new file mode 100644
> index 0000000..136fc52
> --- /dev/null
> +++ b/arch/arm/dts/zynq-brsmarc2-vxworks.dtsi
> @@ -0,0 +1,143 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * primary OS (vxWorks 6.9.4.x) specific parts for B&R BRSMARC2 boards
> + *
> + * Copyright (C) 2019 B&R Industrial Automation GmbH
> + */
> +
> +#include "zynq-brsmarc2-common.dtsi"
> +
> +/ {
> +	fset: factory-settings {
> +		compatible = "bur,fsetv1";
> +		bl-version	= "                                ";
> +		order-no	= "                                ";
> +		cpu-order-no	= "                                ";
> +		hw-revision	= "                                ";
> +		serial-no	= <0>;
> +		device-id	= <0x0>;
> +		parent-id	= <0x0>;
> +		hw-variant	= <0x0>;
> +		hw-platform	= <0x0>;
> +		fram-offset	= <0x0>;
> +		fram-size	= <0x0>;
> +		cache-disable	= <0x0>;
> +		cpu-clock	= <0x0>;
> +	};
> +
> +	aliases {
> +		fset = &fset;
> +	};
> +
> +	board {
> +		status = "okay";
> +		compatible = "bur,brsmarc2-som";
> +		usb0mux-gpios = <&gpio0 68 GPIO_ACTIVE_HIGH>;
> +		usb1mux-gpios = <&gpio0 69 GPIO_ACTIVE_HIGH>;
> +		powerdown-gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
> +		reset-gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
> +	};
> +
> +	fpga: fpga@40000000 {
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		status = "disabled";
> +		compatible = "bur,zynqPL", "simple-bus";
> +		reg = <0x40200000 0x1		/* version registers */
> +		       0x40200004 0x1>;		/* misc registers */
> +		bur,upddest = &spi_flash;
> +		bur,updaddr = <0x100000>;
> +		bur,updsize = <0x200000>;
> +
> +		plk: plk@80000000 {
> +			status = "disabled";
> +			compatible = "bur,DdVxIoEplSMP";
> +			bur,hwtree = "IF9";
> +			reg = <0x80000000 0x8000>;
> +			interrupt-parent = <&intc>;
> +			interrupts = <0 68 4>,
> +				     <0 84 4>;
> +			local-mac-address = [ 00 60 65 aa ab ac ];
> +		};
> +
> +		x2x: x2x@40100000 {
> +			status = "disabled";
> +			compatible = "bur,xlk";
> +			bur,hwtree = "IF10";
> +			reg = <0x40100000 0x8000
> +			       0x40108000 0x8000>;
> +			interrupt-parent = <&intc>;
> +			interrupts = <0 65 4>;
> +		};
> +
> +		uart2: serial@40200800 {
> +			status = "disabled";
> +			compatible = "ns16550a", "bur,DdVxSf16x5xIO";
> +			bur,hwtree = "IF8";
> +			reg = <0x40200800 0x40>;
> +			interrupt-parent = <&intc>;
> +			interrupts = <0 66 4>;
> +			term-gpios = <&gpio0 71 GPIO_ACTIVE_HIGH>;
> +		};
> +
> +		uart3: serial@40200840 {
> +			status = "disabled";
> +			compatible = "ns16550a", "bur,DdVxSf16x5xIO";
> +			bur,hwtree = "IF9";
> +			reg = <0x40200840 0x40>;
> +			interrupt-parent = <&intc>;
> +			interrupts = <0 67 4>;
> +			term-gpios = <&gpio0 71 GPIO_ACTIVE_HIGH>;
> +		};
> +
> +		uart4: serial@40200900 {
> +			status = "disabled";
> +			compatible = "ns16550a", "bur,DdVxSf16x5xIO";
> +			bur,hwtree = "IF20";
> +			reg = <0x40200900 0x40>;
> +			interrupt-parent = <&intc>;
> +			interrupts = <0 88 4>;
> +		};
> +
> +		uart5: serial@40200A00 {
> +			status = "disabled";
> +			compatible = "ns16550a", "bur,DdVxSf16x5xIO";
> +			bur,hwtree = "IF21";
> +			reg = <0x40200A00 0x40>;
> +			interrupt-parent = <&intc>;
> +			interrupts = <0 90 4>;
> +		};
> +	};
> +};
> +
> +&i2c0 {
> +	resetc: reset-controller@60 {
> +		compatible = "bur,rststm";
> +		reg = <0x60>;
> +		hit-gpios = <&gpio0 84 GPIO_ACTIVE_HIGH>;
> +		cooling-min-state = <0>;
> +		cooling-max-state = <1>;	/* reset gets fired */
> +		#cooling-cells = <2>;		/* min followed by max */
> +	};
> +};
> +
> +&can0 {
> +	status = "disabled";
> +	bur,hwtree = "IF6";
> +	term-gpios = <&gpio0 70 GPIO_ACTIVE_HIGH>;
> +};
> +
> +&can1 {
> +	status = "disabled";
> +	bur,hwtree = "IF7";
> +	term-gpios = <&gpio0 71 GPIO_ACTIVE_HIGH>;
> +};
> +
> +&ethernet_phy0 {
> +		ti,ledcr = <0x0480>;
> +		ti,rgmii-rxclk-shift;

fix indentation

> +};
> +
> +&ethernet_phy1 {
> +		ti,ledcr = <0x0480>;


ditto.

> +};
> diff --git a/arch/arm/dts/zynq-brsmarc2.dts b/arch/arm/dts/zynq-brsmarc2.dts
> new file mode 100644
> index 0000000..b53a2e7
> --- /dev/null
> +++ b/arch/arm/dts/zynq-brsmarc2.dts
> @@ -0,0 +1,8 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * B&R BRSMARC2 board DTS file
> + *
> + * Copyright (C) 2019 B&R Industrial Automation GmbH
> + */
> +
> +#include "zynq-brsmarc2-vxworks.dtsi"

if you want to use it in this way I would expect you will do it like this.

#include "zynq-brsmarc2-common.dtsi"
#include "zynq-brsmarc2-vxworks.dtsi"

Where you are saying that you are taking common + vxworks as default.
(And remove -common.dtsi from vxworks file of course).

> diff --git a/board/BuR/zynq/.gitignore b/board/BuR/zynq/.gitignore
> new file mode 100644
> index 0000000..fa64fbc
> --- /dev/null
> +++ b/board/BuR/zynq/.gitignore
> @@ -0,0 +1 @@
> +./ps7_init_gpl.c

Why?

> diff --git a/board/BuR/zynq/MAINTAINERS b/board/BuR/zynq/MAINTAINERS
> new file mode 100644
> index 0000000..c6b3cfb
> --- /dev/null
> +++ b/board/BuR/zynq/MAINTAINERS
> @@ -0,0 +1,6 @@
> +BRSMARC2 BOARD
> +M:	Hannes Schmelzer <hannes.schmelzer@br-automation.com>
> +S:	Maintained
> +F:	board/BuR/zynq/
> +F:	include/configs/brsmarc2.h
> +F:	configs/brsmarc2_defconfig
> diff --git a/board/BuR/zynq/Makefile b/board/BuR/zynq/Makefile
> new file mode 100644
> index 0000000..85a4b77
> --- /dev/null
> +++ b/board/BuR/zynq/Makefile
> @@ -0,0 +1,16 @@
> +# SPDX-License-Identifier: GPL-2.0+
> +#
> +# Copyright (C) 2019 Hannes Schmelzer <oe5hpm@oevsv.at> -
> +# B&R Industrial Automation GmbH - http://www.br-automation.com
> +#
> +
> +hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE) | sed -e 's/zynq-//')
> +
> +obj-y := ../common/common.o
> +obj-y += ../common/br_resetc.o
> +obj-y += $(hw-platform-y)/board.o
> +
> +obj-$(CONFIG_SPL_BUILD) += $(hw-platform-y)/ps7_init_gpl.o
> +
> +# Suppress "warning: function declaration isn't a prototype"
> +CFLAGS_REMOVE_ps7_init_gpl.o := -Wstrict-prototypes
> diff --git a/board/BuR/zynq/brsmarc2/board.c b/board/BuR/zynq/brsmarc2/board.c
> new file mode 100644
> index 0000000..0331087
> --- /dev/null
> +++ b/board/BuR/zynq/brsmarc2/board.c
> @@ -0,0 +1,63 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Board functions for B&R BRSMARC2 Board
> + *
> + * Copyright (C) 2019 Hannes Schmelzer <oe5hpm@oevsv.at>
> + * B&R Industrial Automation GmbH - http://www.br-automation.com
> + *
> + */
> +#include <common.h>
> +#include <fdtdec.h>
> +#include <asm/arch/sys_proto.h>
> +#include <asm/gpio.h>
> +#include <i2c.h>
> +#include "../../common/bur_common.h"
> +#include "../../common/br_resetc.h"
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#ifdef CONFIG_SPL_BUILD
> +int board_init(void)
> +{
> +	/* reset pulse for peripherals */
> +	gpio_request(9, "nRESET_PS_3V3");
> +	gpio_direction_output(9, 1);
> +
> +	return 0;
> +}
> +#else
> +int board_init(void)
> +{
> +	return 0;
> +}
> +#endif
> +
> +int board_late_init(void)
> +{
> +	int rc;
> +	struct udevice *i2cdev;
> +
> +	br_resetc_bmode();
> +	brdefaultip_setup(0, 0x57);
> +
> +	rc = i2c_get_chip_for_busnum(0, 0x5D, 1, &i2cdev);
> +	if (rc >= 0)
> +		rc = dm_i2c_write(i2cdev, 0xEF, NULL, 0);

IMHO 0x57/0x5D and 0xEF are all magic values and they should be macros
or at least comments what that means.

> +	if (rc != 0)
> +		printf("WARN: cannot write to LEDs!\n");
> +
> +	return 0;
> +}
> +
> +int dram_init(void)
> +{
> +	if (fdtdec_setup_mem_size_base() != 0)
> +		return -EINVAL;
> +
> +	/* simple test if ram_size determined from fdt is plausible */
> +	gd->ram_size = get_ram_size((void *)gd->ram_base, gd->ram_size);
> +
> +	zynq_ddrc_init();
> +
> +	return 0;
> +}
> diff --git a/board/BuR/zynq/brsmarc2/ps7_init_gpl.c b/board/BuR/zynq/brsmarc2/ps7_init_gpl.c
> new file mode 100644
> index 0000000..d4e20d9
> --- /dev/null
> +++ b/board/BuR/zynq/brsmarc2/ps7_init_gpl.c
> @@ -0,0 +1,276 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +#include <asm/arch/ps7_init_gpl.h>
> +
> +unsigned long ps7_pll_init_data_3_0[] = {
> +	EMIT_WRITE(0XF8000008, 0x0000DF0DU),
> +	EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x000FA220U),
> +	EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x00028000U),
> +	EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
> +	EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
> +	EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
> +	EMIT_MASKPOLL(0XF800010C, 0x00000001U),
> +	EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
> +	EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
> +	EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x0012C220U),
> +	EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00020000U),
> +	EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
> +	EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
> +	EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
> +	EMIT_MASKPOLL(0XF800010C, 0x00000002U),
> +	EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
> +	EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
> +	EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001452C0U),
> +	EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x0001E000U),
> +	EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
> +	EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
> +	EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
> +	EMIT_MASKPOLL(0XF800010C, 0x00000004U),
> +	EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
> +	EMIT_WRITE(0XF8000004, 0x0000767BU),
> +	EMIT_EXIT(),
> +};
> +
> +unsigned long ps7_clock_init_data_3_0[] = {
> +	EMIT_WRITE(0XF8000008, 0x0000DF0DU),
> +	EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00700F01U),
> +	EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U),
> +	EMIT_MASKWRITE(0XF800013C, 0x00000011U, 0x00000011U),
> +	EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00500801U),
> +	EMIT_MASKWRITE(0XF8000144, 0x03F03F71U, 0x00500141U),
> +	EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U),
> +	EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00000A01U),
> +	EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A01U),
> +	EMIT_MASKWRITE(0XF8000158, 0x00003F33U, 0x00000503U),
> +	EMIT_MASKWRITE(0XF800015C, 0x03F03F33U, 0x00501903U),
> +	EMIT_MASKWRITE(0XF8000160, 0x007F007FU, 0x00000000U),
> +	EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U),
> +	EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00400500U),
> +	EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
> +	EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01DFC4CDU),
> +	EMIT_WRITE(0XF8000004, 0x0000767BU),
> +	EMIT_EXIT(),
> +};
> +
> +unsigned long ps7_ddr_init_data_3_0[] = {
> +	EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U),
> +	EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU, 0x00001040U),
> +	EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
> +	EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
> +	EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
> +	EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004159AU),
> +	EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44D258D4U),
> +	EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0xB2024127U),
> +	EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU, 0x2B08B290U),
> +	EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U, 0x00000000U),
> +	EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
> +	EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000018U),
> +	EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040970U),
> +	EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x000116D4U),
> +	EMIT_MASKWRITE(0XF8006038, 0x00000003U, 0x00000000U),
> +	EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U),
> +	EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U),
> +	EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0FF66666U),
> +	EMIT_MASKWRITE(0XF8006048, 0x0003F03FU, 0x0003C008U),
> +	EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
> +	EMIT_MASKWRITE(0XF8006058, 0x00010000U, 0x00000000U),
> +	EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
> +	EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
> +	EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
> +	EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284545U),
> +	EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
> +	EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U),
> +	EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U),
> +	EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
> +	EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
> +	EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
> +	EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
> +	EMIT_MASKWRITE(0XF80060B4, 0x00000200U, 0x00000200U),
> +	EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x0020006AU),
> +	EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
> +	EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
> +	EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
> +	EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
> +	EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
> +	EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
> +	EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU, 0x40000001U),
> +	EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU, 0x40000001U),
> +	EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU, 0x40000001U),
> +	EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU, 0x40000001U),
> +	EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x0001D400U),
> +	EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x0001C400U),
> +	EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x0001BC00U),
> +	EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x0001C800U),
> +	EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
> +	EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
> +	EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
> +	EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
> +	EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x0000007AU),
> +	EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007DU),
> +	EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x00000080U),
> +	EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x0000007EU),
> +	EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000CAU),
> +	EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000C6U),
> +	EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000C4U),
> +	EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000C7U),
> +	EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000BAU),
> +	EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BDU),
> +	EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000C0U),
> +	EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000BEU),
> +	EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU, 0x00040080U),
> +	EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FD04U),
> +	EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
> +	EMIT_MASKWRITE(0XF8006208, 0x000703FFU, 0x000003FFU),
> +	EMIT_MASKWRITE(0XF800620C, 0x000703FFU, 0x000003FFU),
> +	EMIT_MASKWRITE(0XF8006210, 0x000703FFU, 0x000003FFU),
> +	EMIT_MASKWRITE(0XF8006214, 0x000703FFU, 0x000003FFU),
> +	EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
> +	EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
> +	EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
> +	EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
> +	EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U, 0x00000000U),
> +	EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
> +	EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
> +	EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A8U),
> +	EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
> +	EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U),
> +	EMIT_MASKPOLL(0XF8006054, 0x00000007U),
> +	EMIT_EXIT(),
> +};
> +
> +unsigned long ps7_mio_init_data_3_0[] = {
> +	EMIT_WRITE(0XF8000008, 0x0000DF0DU),
> +	EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
> +	EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
> +	EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
> +	EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U),
> +	EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
> +	EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U),
> +	EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
> +	EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C068U),
> +	EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F98068U),
> +	EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F98068U),
> +	EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F98068U),
> +	EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000260U),
> +	EMIT_MASKWRITE(0XF8000B70, 0x00000001U, 0x00000001U),
> +	EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
> +	EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU, 0x00000823U),
> +	EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00000700U),
> +	EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U),
> +	EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U),
> +	EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U),
> +	EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U),
> +	EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U),
> +	EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U),
> +	EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000700U),
> +	EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U),
> +	EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00000700U),
> +	EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x000007A0U),
> +	EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x000007A0U),
> +	EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x000007A0U),
> +	EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x000007A0U),
> +	EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x000016E1U),
> +	EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x000006E0U),
> +	EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00000302U),
> +	EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00000302U),
> +	EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00000302U),
> +	EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00000302U),
> +	EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00000302U),
> +	EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00000302U),
> +	EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000303U),
> +	EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000303U),
> +	EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000303U),
> +	EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000303U),
> +	EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000303U),
> +	EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000303U),
> +	EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000204U),
> +	EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000205U),
> +	EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000204U),
> +	EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000205U),
> +	EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000204U),
> +	EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000204U),
> +	EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000204U),
> +	EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000204U),
> +	EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000205U),
> +	EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000204U),
> +	EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000204U),
> +	EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000204U),
> +	EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U),
> +	EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U),
> +	EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U),
> +	EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U),
> +	EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U),
> +	EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U),
> +	EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00000321U),
> +	EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU, 0x00000320U),
> +	EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x00000320U),
> +	EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x00000321U),
> +	EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x00000340U),
> +	EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x00000340U),
> +	EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000280U),
> +	EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000280U),
> +	EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x00380037U),
> +	EMIT_WRITE(0XF8000004, 0x0000767BU),
> +	EMIT_EXIT(),
> +};
> +
> +unsigned long ps7_peripherals_init_data_3_0[] = {
> +	EMIT_WRITE(0XF8000008, 0x0000DF0DU),
> +	EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
> +	EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U),
> +	EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
> +	EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
> +	EMIT_WRITE(0XF8000004, 0x0000767BU),
> +	EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U),
> +	EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU),
> +	EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U),
> +	EMIT_MASKWRITE(0XE0000004, 0x000003FFU, 0x00000020U),
> +	EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
> +	EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
> +	EMIT_MASKDELAY(0XF8F00200, 1),
> +	EMIT_MASKDELAY(0XF8F00200, 1),
> +	EMIT_MASKDELAY(0XF8F00200, 1),
> +	EMIT_MASKDELAY(0XF8F00200, 1),
> +	EMIT_MASKDELAY(0XF8F00200, 1),
> +	EMIT_MASKDELAY(0XF8F00200, 1),
> +	EMIT_EXIT(),
> +};
> +
> +unsigned long ps7_post_config_3_0[] = {
> +	EMIT_WRITE(0XF8000008, 0x0000DF0DU),
> +	EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
> +	EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
> +	EMIT_WRITE(0XF8000004, 0x0000767BU),
> +	EMIT_EXIT(),
> +};
> +
> +int ps7_post_config(void)
> +{
> +	return ps7_config(ps7_post_config_3_0);
> +}
> +
> +int ps7_init(void)
> +{
> +	int ret;
> +
> +	ret = ps7_config(ps7_mio_init_data_3_0);
> +	if (ret != PS7_INIT_SUCCESS)
> +		return ret;
> +
> +	ret = ps7_config(ps7_pll_init_data_3_0);
> +	if (ret != PS7_INIT_SUCCESS)
> +		return ret;
> +
> +	ret = ps7_config(ps7_clock_init_data_3_0);
> +	if (ret != PS7_INIT_SUCCESS)
> +		return ret;
> +
> +	ret = ps7_config(ps7_ddr_init_data_3_0);
> +	if (ret != PS7_INIT_SUCCESS)
> +		return ret;
> +
> +	ret = ps7_config(ps7_peripherals_init_data_3_0);
> +	if (ret != PS7_INIT_SUCCESS)
> +		return ret;
> +
> +	return PS7_INIT_SUCCESS;
> +}
> diff --git a/board/BuR/zynq/config.mk b/board/BuR/zynq/config.mk
> new file mode 100644
> index 0000000..17e3d57
> --- /dev/null
> +++ b/board/BuR/zynq/config.mk
> @@ -0,0 +1,49 @@
> +# SPDX-License-Identifier:	GPL-2.0+
> +#
> +# Copyright (C) 2019 Hannes Schmelzer <oe5hpm@oevsv.at> -
> +# B&R Industrial Automation GmbH - http://www.br-automation.com
> +#
> +
> +hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE) | sed -e 's/zynq-//')
> +
> +payload_off :=$(shell printf "%d" $(CONFIG_SYS_SPI_U_BOOT_OFFS))
> +
> +fpga_path := $(shell echo $(KBUILD_SRC)/board/$(BOARDDIR)/$(hw-platform-y))
> +fpga_src  := $(shell ls $(fpga_path)/*.bit 2>/dev/null)
> +fpga_file := $(shell echo $(fpga_src) | rev | cut -d/ -f1 | rev)
> +fpga_off  := $(shell printf "%d" \
> +	     $(shell cat $(fpga_path)/${fpga_file}.offset 2>/dev/null))
> +flen_min  := $(shell expr ${payload_off} + ${fpga_off})
> +
> +quiet_cmd_prodbin = PRODBIN $@ $(payload_off)
> +cmd_prodbin = \
> +	dd if=/dev/zero bs=1 count=${flen_min} 2>/dev/null | tr "\000" "\377" >$@ && \
> +	dd conv=notrunc bs=1 if=spl/boot.bin of=$@ seek=0 2>/dev/null && \
> +	test -z ${fpga_src} && dd conv=notrunc bs=1 if=u-boot-dtb.img of=$@ seek=$(payload_off) 2>/dev/null && \
> +	test -z ${fpga_src} || ( \
> +		dd conv=notrunc bs=1 if=u-boot-dtb.img of=$@ seek=$(payload_off) 2>/dev/null; \
> +		dd obs=1 if=$(fpga_file) of=$@ seek=$(fpga_off) 2>/dev/null \
> +		)
> +
> +quiet_cmd_prodzip = SAPZIP  $@
> +cmd_prodzip =					\
> +	test -d misc && rm -r misc;		\
> +	mkdir misc &&				\
> +	cp spl/boot.bin misc/ &&		\
> +	cp u-boot-dtb.img misc/ &&		\
> +	zip -9 -r $@ misc/* >/dev/null $<
> +
> +quiet_cmd_fpga = FPGA    $@ ($(fpga_file)) @ $(fpga_off)
> +cmd_fpga = test -z ${fpga_src} || cp ${fpga_src} $(fpga_file)
> +
> +$(hw-platform-y)_fpga:
> +	$(call if_changed,fpga)
> +
> +$(hw-platform-y)_prog.bin: u-boot-dtb.img spl/boot.bin $(hw-platform-y)_fpga
> +	$(call if_changed,prodbin)
> +
> +$(hw-platform-y)_prod.zip: $(hw-platform-y)_prog.bin
> +	$(call if_changed,prodzip)
> +
> +

one newline is enought.

> +ALL-y += $(hw-platform-y)_prod.zip
> diff --git a/configs/brsmarc2_defconfig b/configs/brsmarc2_defconfig
> new file mode 100644
> index 0000000..b325eeb
> --- /dev/null
> +++ b/configs/brsmarc2_defconfig
> @@ -0,0 +1,75 @@
> +CONFIG_ARM=y
> +CONFIG_SYS_VENDOR="BuR"
> +CONFIG_SYS_CONFIG_NAME="brsmarc2"
> +CONFIG_ARCH_ZYNQ=y
> +CONFIG_SYS_TEXT_BASE=0x4000000
> +CONFIG_SPL_GPIO_SUPPORT=y
> +# CONFIG_SPL_MMC_SUPPORT is not set
> +CONFIG_ENV_SIZE=0x10000
> +CONFIG_ENV_OFFSET=0x20000
> +CONFIG_NR_DRAM_BANKS=1
> +CONFIG_SPL=y
> +CONFIG_ZYNQ_SDHCI_MAX_FREQ=100000000
> +CONFIG_OF_BOARD_SETUP=y
> +CONFIG_BOOTDELAY=0
> +CONFIG_USE_BOOTCOMMAND=y
> +CONFIG_BOOTCOMMAND="run b_default"
> +# CONFIG_DISPLAY_CPUINFO is not set
> +# CONFIG_SPL_RAM_SUPPORT is not set
> +CONFIG_HUSH_PARSER=y
> +# CONFIG_CMD_BOOTD is not set
> +CONFIG_CMD_BOOTZ=y
> +# CONFIG_CMD_IMI is not set
> +# CONFIG_CMD_XIMG is not set
> +# CONFIG_CMD_EXPORTENV is not set
> +# CONFIG_CMD_IMPORTENV is not set
> +# CONFIG_CMD_EDITENV is not set
> +# CONFIG_CMD_ENV_EXISTS is not set
> +# CONFIG_CMD_CRC32 is not set
> +# CONFIG_CMD_FLASH is not set
> +CONFIG_CMD_FPGA_LOADFS=y
> +CONFIG_CMD_GPIO=y
> +CONFIG_CMD_I2C=y
> +# CONFIG_CMD_LOADB is not set
> +# CONFIG_CMD_LOADS is not set
> +CONFIG_CMD_MMC=y
> +CONFIG_CMD_SF=y
> +CONFIG_CMD_USB=y
> +CONFIG_CMD_DHCP=y
> +# CONFIG_CMD_NFS is not set
> +CONFIG_CMD_MII=y
> +CONFIG_CMD_PING=y
> +CONFIG_CMD_CACHE=y
> +CONFIG_CMD_TIME=y
> +# CONFIG_CMD_MISC is not set
> +CONFIG_CMD_EXT4=y
> +CONFIG_CMD_EXT4_WRITE=y
> +CONFIG_CMD_FAT=y
> +CONFIG_CMD_FS_GENERIC=y
> +# CONFIG_SPL_DOS_PARTITION is not set
> +CONFIG_DEFAULT_DEVICE_TREE="zynq-brsmarc2"
> +CONFIG_ENV_IS_IN_SPI_FLASH=y
> +CONFIG_ENV_SECT_SIZE=0x10000
> +CONFIG_NET_RANDOM_ETHADDR=y
> +CONFIG_SPL_DM_SEQ_ALIAS=y
> +CONFIG_FPGA_XILINX=y
> +CONFIG_FPGA_ZYNQPL=y
> +CONFIG_DM_GPIO=y
> +CONFIG_DM_I2C=y
> +CONFIG_SYS_I2C_CADENCE=y
> +CONFIG_MMC_SDHCI=y
> +CONFIG_MMC_SDHCI_ZYNQ=y
> +CONFIG_SPI_FLASH=y
> +CONFIG_SF_DEFAULT_SPEED=30000000
> +CONFIG_SPI_FLASH_SPANSION=y
> +CONFIG_PHY_NATSEMI=y
> +CONFIG_MII=y
> +CONFIG_ZYNQ_GEM=y
> +CONFIG_ZYNQ_SERIAL=y
> +CONFIG_ZYNQ_QSPI=y
> +CONFIG_USB=y
> +CONFIG_USB_EHCI_HCD=y
> +CONFIG_USB_ULPI_VIEWPORT=y
> +CONFIG_USB_ULPI=y
> +CONFIG_USB_STORAGE=y
> +# CONFIG_EFI_LOADER is not set
> diff --git a/include/configs/brsmarc2.h b/include/configs/brsmarc2.h
> new file mode 100644
> index 0000000..0b37fcc
> --- /dev/null
> +++ b/include/configs/brsmarc2.h
> @@ -0,0 +1,150 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * specific parts for B&R brsmarc2 SoM
> + *
> + * Copyright (C) 2019 Hannes Schmelzer <oe5hpm@oevsv.at> -
> + * B&R Industrial Automation GmbH - http://www.br-automation.com
> + *
> + */
> +
> +#ifndef __CONFIG_BRSMARC2_H__
> +#define __CONFIG_BRSMARC2_H__
> +
> +#include <configs/bur_cfg_common.h>
> +
> +/* Cache options */
> +#define CONFIG_SYS_L2CACHE_OFF
> +#ifndef CONFIG_SYS_L2CACHE_OFF
> +# define CONFIG_SYS_L2_PL310
> +# define CONFIG_SYS_PL310_BASE		0xf8f02000
> +#endif
> +
> +#define ZYNQ_SCUTIMER_BASEADDR		0xF8F00600
> +#define CONFIG_SYS_TIMERBASE		ZYNQ_SCUTIMER_BASEADDR
> +#define CONFIG_SYS_TIMER_COUNTS_DOWN
> +#define CONFIG_SYS_TIMER_COUNTER	(CONFIG_SYS_TIMERBASE + 0x4)
> +
> +/* Serial drivers */
> +#define CONFIG_BAUDRATE		115200

This is in Kconfig already.

> +/* The following table includes the supported baudrates */
> +#define CONFIG_SYS_BAUDRATE_TABLE  \
> +	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}

All these configs L2/timer included are already in zynq-common.dtsi.
I think I told you to include this file here. If there is something what
you don't want to enable for your board then let's fix it but I really
don't like to c&p setting which is already written. It is purely
duplication for no reason.
This file should include zynq-common.dtsi and take configuration from
that file. If there is something board specific then we should find a
way how to fix this.

> +
> +/* MMC */
> +#define CONFIG_ZYNQ_HISPD_BROKEN
> +
> +/* USB */
> +#define CONFIG_EHCI_IS_TDI
> +#define CONFIG_USB_MAX_CONTROLLER_COUNT	1
> +
> +/* Environment */
> +#define CONFIG_SYS_AUTOLOAD	"no"

I have not a problem with listing things like this because it takes time
to move things to Kconfig but copying baseaddresses and setting for SPL
doesn't make sense.

> +
> +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
> +#define CONFIG_ENV_OFFSET_REDUND		(CONFIG_ENV_OFFSET + \
> +						 CONFIG_ENV_SECT_SIZE)
> +#define CONFIG_EXTRA_ENV_SETTINGS	\
> +BUR_COMMON_ENV \
> +"board_id=0xFF\0" \
> +"scradr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
> +"dtbaddr=0x4000000\0" \
> +"loadaddr=0x2000000\0" \
> +"fpgaaddr=fdt get value fpgabase /fpga bur,updaddr;" \
> +" fdt get value fpgasize /fpga bur,updsize\0" \
> +"fpga=setenv fpgastatus disabled; run fpgaaddr;" \
> +" sf read ${loadaddr} ${fpgabase} ${fpgasize} &&" \
> +" fpga loadb 0 ${loadaddr} ${fpgasize} && setenv fpgastatus okay\0" \
> +"fpgastatus=disabled\0" \
> +"fpgaupd=run fpgaaddr && tftp ${loadaddr} X20CP04xx.bit &&" \
> +" sf erase ${fpgabase} +${filesize} &&" \
> +" sf write ${loadaddr} ${fpgabase} ${filesize}\0" \
> +"netupd=tftp ${loadaddr} boot.bin && sf probe &&" \
> +" sf erase 0 +${filesize} && sf write ${loadaddr} 0 ${filesize} &&" \
> +" tftp ${loadaddr} u-boot-dtb.img &&" \
> +" sf erase 0x40000 +${filesize} && sf write ${loadaddr} 0x40000 ${filesize}\0" \
> +"cfgscr=mw ${dtbaddr} 0;" \
> +" sf probe && sf read ${scradr} 0xC0000 0x10000 && source ${scradr};" \
> +" fdt addr ${dtbaddr} || cp ${fdtcontroladdr} ${dtbaddr} 4000\0" \
> +"vxargs=setenv bootargs gem(0,0)host:vxWorks h=${serverip}" \
> +" e=${ipaddr}:${netmask} g=${gatewayip} u=vxWorksFTP pw=vxWorks\0" \
> +"vxfdt=fdt addr ${dtbaddr}; fdt resize 0x10000;" \
> +" fdt set /fpga status ${fpgastatus};" \
> +" fdt boardsetup\0" \
> +"startvx=run vxargs && mw 0x1100 0 && run vxfdt &&" \
> +" bootm ${loadaddr} - ${dtbaddr}\0" \
> +"b_break=0\0" \
> +"b_tgts_std=mmc spi usb0 net0 net1\0" \
> +"b_tgts_rcy=spi usb0 net0 net1\0" \
> +"b_tgts_pme=usb0 net0 net1 mmc spi\0" \
> +"b_deftgts=if test ${b_mode} = 12; then setenv b_tgts ${b_tgts_pme};" \
> +" elif test ${b_mode} = 0; then setenv b_tgts ${b_tgts_rcy};" \
> +" else setenv b_tgts ${b_tgts_std}; fi\0" \
> +"b_mmc=run fpga; mmc dev 0; load mmc 0 ${loadaddr} arimg && run startvx\0" \
> +"b_spi=run fpga; sf read ${loadaddr} 900000 700000 && run startvx\0" \
> +"b_net0=tftp ${scradr} netscr-brsmarc2-${board_id}.img && source ${scradr}\0" \
> +"b_net1=tftp ${scradr} netscript.img && source ${scradr}\0" \
> +"b_usb0=usb start && load usb 0 ${scradr} bootscr.img && source ${scradr}\0" \
> +"b_default=run b_deftgts; for target in ${b_tgts};"\
> +" do run b_${target}; if test ${b_break} = 1; then; exit; fi; done\0"
> +
> +#define CONFIG_SYS_LOAD_ADDR		0xC0000	/*
> +						 * default load and execution
> +						 * address for loads / scripts
> +						 */
> +/* Support both device trees and ATAGs. */
> +#define CONFIG_CMDLINE_TAG
> +#define CONFIG_SETUP_MEMORY_TAGS
> +#define CONFIG_INITRD_TAG
> +#define CONFIG_MACH_TYPE		0xFFFFFFFF
> +
> +/* Miscellaneous configurable options */
> +#define CONFIG_CLOCKS
> +#define CONFIG_SYS_CONSOLE_INFO_QUIET
> +#define CONFIG_SYS_BOOTM_LEN		(32 * 1024 * 1024)
> +/* Physical Memory map */
> +#define CONFIG_SYS_TEXT_BASE		0x4000000
> +
> +#define CONFIG_SYS_SDRAM_BASE		0
> +
> +#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
> +#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x1000)
> +
> +#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_SDRAM_BASE
> +#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_MALLOC_LEN
> +#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
> +					CONFIG_SYS_INIT_RAM_SIZE - \
> +					GENERATED_GBL_DATA_SIZE)
> +
> +#define CONFIG_SYS_SPI_U_BOOT_OFFS	0x40000
> +/* SPL part */
> +#ifdef CONFIG_SPL_BUILD
> +#define CONFIG_SPL_I2C_SUPPORT
> +
> +/* Disable dcache for SPL just for sure */
> +#define CONFIG_SYS_DCACHE_OFF
> +
> +#ifdef CONFIG_ZYNQ_QSPI
> +# define CONFIG_SPL_SPI_LOAD
> +#endif /* CONFIG_ZYNQ_QSPI */
> +
> +/* SP location before relocation, must use scratch RAM */
> +#define CONFIG_SPL_TEXT_BASE		0x0
> +/* 3 * 64kB blocks of OCM - one is on the top because of bootrom */
> +#define CONFIG_SPL_MAX_SIZE		0x30000
> +/* The highest 64k OCM address */
> +#define OCM_HIGH_ADDR			0xffff0000
> +/* Just define any reasonable size */
> +#define CONFIG_SPL_STACK_SIZE		0x2000
> +/* SPL stack position - and stack goes down */
> +#define CONFIG_SPL_STACK		(OCM_HIGH_ADDR + CONFIG_SPL_STACK_SIZE)
> +/* On the top of OCM space */
> +#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SPL_STACK + \
> +					 GENERATED_GBL_DATA_SIZE)
> +
> +#define CONFIG_SYS_SPL_MALLOC_SIZE	0x8000
> +/* BSS setup */
> +#define CONFIG_SPL_BSS_START_ADDR	0x100000
> +#define CONFIG_SPL_BSS_MAX_SIZE		0x100000
> +#define CONFIG_SYS_UBOOT_START		CONFIG_SYS_TEXT_BASE
> +#endif /* CONFIG_SPL_BUILD */
> +#endif /* __CONFIG_BRSMARC2_H__ */
> 

Thanks,
Michal
Hannes Schmelzer Aug. 22, 2019, 7:58 a.m. UTC | #2 
"Michal Simek" <monstr@monstr.eu> wrote on 14.08.2019 08:10:31:

> 
> Hi,
> 
> first of all sorry for delay I had vacation.
Hi Michal,
thanks for your time again. I'm now working again on u-boot and 
zynq-board.

> > +
> > +   memory {
> > +      device_type = "memory";
> > +      reg = <0x0 0x20000000>;
> > +   };
> > +
> > +   chosen {
> > +      bootargs = "console=ttyPS0,115200 earlyprintk";
> 
> This looks like as Linux command line. If yes you should use earlycon
> instead of earlyprintk which is used for debugging.

yes, will do so in v6


> > +
> > +&ethernet_phy0 {
> > +      ti,ledcr = <0x0480>;
> > +      ti,rgmii-rxclk-shift;
> 
> fix indentation
> 
> > +};
> > +
> > +&ethernet_phy1 {
> > +      ti,ledcr = <0x0480>;
> 
> 
> ditto.

gets fixed in v6.

> 
> > +};
> > diff --git a/arch/arm/dts/zynq-brsmarc2.dts 
b/arch/arm/dts/zynq-brsmarc2.dts
> > new file mode 100644
> > index 0000000..b53a2e7
> > --- /dev/null
> > +++ b/arch/arm/dts/zynq-brsmarc2.dts
> > @@ -0,0 +1,8 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * B&R BRSMARC2 board DTS file
> > + *
> > + * Copyright (C) 2019 B&R Industrial Automation GmbH
> > + */
> > +
> > +#include "zynq-brsmarc2-vxworks.dtsi"
> 
> if you want to use it in this way I would expect you will do it like 
this.
> 
> #include "zynq-brsmarc2-common.dtsi"
> #include "zynq-brsmarc2-vxworks.dtsi"
> 
> Where you are saying that you are taking common + vxworks as default.
> (And remove -common.dtsi from vxworks file of course).

gets fixed in v6.

> 
> > diff --git a/board/BuR/zynq/.gitignore b/board/BuR/zynq/.gitignore
> > new file mode 100644
> > index 0000000..fa64fbc
> > --- /dev/null
> > +++ b/board/BuR/zynq/.gitignore
> > @@ -0,0 +1 @@
> > +./ps7_init_gpl.c
> 
> Why?
no reason for that, some artifact from early days.
so dropping it in v6.


> > +
> > +int board_late_init(void)
> > +{
> > +   int rc;
> > +   struct udevice *i2cdev;
> > +
> > +   br_resetc_bmode();
> > +   brdefaultip_setup(0, 0x57);
> > +
> > +   rc = i2c_get_chip_for_busnum(0, 0x5D, 1, &i2cdev);
> > +   if (rc >= 0)
> > +      rc = dm_i2c_write(i2cdev, 0xEF, NULL, 0);
> 
> IMHO 0x57/0x5D and 0xEF are all magic values and they should be macros
> or at least comments what that means.

adding some comments with description about whats going on in v6.

> > +$(hw-platform-y)_prod.zip: $(hw-platform-y)_prog.bin
> > +   $(call if_changed,prodzip)
> > +
> > +
> 
> one newline is enought.

will be fixed in v6.


> > --- /dev/null
> > +++ b/include/configs/brsmarc2.h
> > @@ -0,0 +1,150 @@
> > +/* SPDX-License-Identifier: GPL-2.0+ */
> > +/*
> > + * specific parts for B&R brsmarc2 SoM
> > + *
> > + * Copyright (C) 2019 Hannes Schmelzer <oe5hpm@oevsv.at> -
> > + * B&R Industrial Automation GmbH - http://www.br-automation.com
> > + *
> > + */
> > +
> > +#ifndef __CONFIG_BRSMARC2_H__
> > +#define __CONFIG_BRSMARC2_H__
> > +
> > +#include <configs/bur_cfg_common.h>
> > +
> > +/* Cache options */
> > +#define CONFIG_SYS_L2CACHE_OFF
> > +#ifndef CONFIG_SYS_L2CACHE_OFF
> > +# define CONFIG_SYS_L2_PL310
> > +# define CONFIG_SYS_PL310_BASE      0xf8f02000
> > +#endif
> > +
> > +#define ZYNQ_SCUTIMER_BASEADDR      0xF8F00600
> > +#define CONFIG_SYS_TIMERBASE      ZYNQ_SCUTIMER_BASEADDR
> > +#define CONFIG_SYS_TIMER_COUNTS_DOWN
> > +#define CONFIG_SYS_TIMER_COUNTER   (CONFIG_SYS_TIMERBASE + 0x4)
> > +
> > +/* Serial drivers */
> > +#define CONFIG_BAUDRATE      115200
> 
> This is in Kconfig already.

ok, dropping it here in v6.

> 
> > +/* The following table includes the supported baudrates */
> > +#define CONFIG_SYS_BAUDRATE_TABLE  \
> > +   {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 
230400}
> 
> All these configs L2/timer included are already in zynq-common.dtsi.
> I think I told you to include this file here. If there is something what
> you don't want to enable for your board then let's fix it but I really
> don't like to c&p setting which is already written. It is purely
> duplication for no reason.
> This file should include zynq-common.dtsi and take configuration from
> that file. If there is something board specific then we should find a
> way how to fix this.
> 

this looks like to be the last big challenge to get rid with my new board 
;-)

I think you mean zynq-common.h

Yes, you told me using it ... more than one time ... but i'm still very 
unhappy
with this zynq-common.h since it is very overloaded and trimmed to
the existing eval-boards.

Maybe we have a chance to split the zynq-common.h up into at least
two parts where having at one side all soc-specific stuff (various
base-addresses, caching, timer, stack, ....), the bare-minimum and
at the other side all "application-specific", meaning distro-default,
bootcommand, filenames, boot-devices, load-addresses ...

This would give us the opportunity having boards like the existing
eval-boards and boards like mine which loving the bare minimum.

hw?

> > +
> > +/* Environment */
> > +#define CONFIG_SYS_AUTOLOAD   "no"
> 
> I have not a problem with listing things like this because it takes time
> to move things to Kconfig but copying baseaddresses and setting for SPL
> doesn't make sense.

no glue at the moment. pls a bit more explanation.

> > 
> 
> Thanks,
> Michal

cheers,
Hannes
Michal Simek Aug. 22, 2019, 8:10 a.m. UTC | #3 
>> > +/* The following table includes the supported baudrates */
>> > +#define CONFIG_SYS_BAUDRATE_TABLE  \
>> > +   {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
>> 
>> All these configs L2/timer included are already in zynq-common.dtsi.
>> I think I told you to include this file here. If there is something what
>> you don't want to enable for your board then let's fix it but I really
>> don't like to c&p setting which is already written. It is purely
>> duplication for no reason.
>> This file should include zynq-common.dtsi and take configuration from
>> that file. If there is something board specific then we should find a
>> way how to fix this.
>> 
> 
> this looks like to be the last big challenge to get rid with my new
> board ;-)
> 
> I think you mean zynq-common.h
> 
> Yes, you told me using it ... more than one time ... but i'm still very
> unhappy
> with this zynq-common.h since it is very overloaded and trimmed to
> the existing eval-boards.
> 
> Maybe we have a chance to split the zynq-common.h up into at least
> two parts where having at one side all soc-specific stuff (various
> base-addresses, caching, timer, stack, ....), the bare-minimum and
> at the other side all "application-specific", meaning distro-default,
> bootcommand, filenames, boot-devices, load-addresses ...
> 
> This would give us the opportunity having boards like the existing
> eval-boards and boards like mine which loving the bare minimum.


This sounds like c&p thing which should be quite fast. Feel free to do
it and we can discuss if this is ok or not. Especially where that split
should be and why some macros should be moved there or there.
Till now if there was any need we have added #ifndef XXX and redefine it
in board file.
From u-boot project point of view if there is real need to change these
things then we should look at moving them to Kconfig first and current
values should be default that you can simply rewrite it.

>> > +
>> > +/* Environment */
>> > +#define CONFIG_SYS_AUTOLOAD   "no"
>> 
>> I have not a problem with listing things like this because it takes time
>> to move things to Kconfig but copying baseaddresses and setting for SPL
>> doesn't make sense.
> 
> no glue at the moment. pls a bit more explanation.

Normally when you convert one option to Kconfig then you should fix all
boards which takes a lot of time and a lot of effort because multiple
targets need to be checked.
It is easier just to introduce Kconfig and limit it's scope for certain
SoC and let others to extend it till everything is converted and
limitation can be removed.

I will be checking that "board" specific macros one by one to see what
we can do with it.

Thanks,
Michal
diff mbox series

Patch

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 20dbc2f..e718fe6 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -233,6 +233,7 @@  dtb-$(CONFIG_ARCH_ZYNQ) += \
 	zynq-zc770-xm011-x16.dtb \
 	zynq-zc770-xm012.dtb \
 	zynq-zc770-xm013.dtb \
+	zynq-brsmarc2.dtb \
 	zynq-zed.dtb \
 	zynq-zturn.dtb \
 	zynq-zybo.dtb \
diff --git a/arch/arm/dts/zynq-brsmarc2-common.dtsi b/arch/arm/dts/zynq-brsmarc2-common.dtsi
new file mode 100644
index 0000000..09b88c7
--- /dev/null
+++ b/arch/arm/dts/zynq-brsmarc2-common.dtsi
@@ -0,0 +1,157 @@ 
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * common DTS part for B&R BRSMARC2 boards
+ *
+ * Copyright (C) 2019 B&R Industrial Automation GmbH
+ */
+
+/dts-v1/;
+#include "zynq-7000.dtsi"
+#include <dt-bindings/thermal/thermal.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	model = "BRSMARC2 Zynq SoM";
+	compatible = "xlnx,zynq-7000";
+
+	aliases {
+		ethernet0 = &gem0;
+		ethernet1 = &gem1;
+		i2c0 = &i2c0;
+		serial0 = &uart0;
+		spi0 = &qspi;
+		mmc0 = &sdhci0;
+		can0 = &can0;
+		can1 = &can1;
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x0 0x20000000>;
+	};
+
+	chosen {
+		bootargs = "console=ttyPS0,115200 earlyprintk";
+		stdout-path = "serial0:115200n8";
+	};
+
+	usb_phy0: phy0 {
+		compatible = "usb-nop-xceiv";
+		#phy-cells = <0>;
+	};
+
+	board_thermal: board-thermal {
+		polling-delay-passive = <1000>; /* milliseconds */
+		polling-delay = <2500>; /* milliseconds */
+
+		thermal-sensors = <&temp_core 0>;
+
+		trips {
+			crit_trip: crit-trip {
+				temperature = <100000>; /* millicelsius */
+				hysteresis = <5000>; /* millicelsius */
+				type = "critical";
+			};
+		};
+		cooling-maps {
+			map0 {
+				trip = <&crit_trip>;
+				cooling-device =
+				<&resetc THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+			};
+		};
+	};
+};
+
+&amba {
+	ocm: sram@fffc0000 {
+		compatible = "mmio-sram";
+		reg = <0xfffc0000 0x10000>;
+	};
+};
+
+&clkc {
+	ps-clk-frequency = <33333333>;
+};
+
+&gem0 {
+	status = "okay";
+	phy-mode = "rgmii-id";
+	phy-handle = <&ethernet_phy0>;
+
+	/* DP83822 phy */
+	ethernet_phy0: ethernet-phy@1 {
+		reg = <1>;
+	};
+};
+
+&gem1 {
+	status = "okay";
+	phy-mode = "rgmii-id";
+	phy-handle = <&ethernet_phy1>;
+
+	/* DP83822 phy */
+	ethernet_phy1: ethernet-phy@3 {
+		reg = <3>;
+	};
+};
+
+&i2c0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+	clock-frequency = <100000>;
+
+	boardtemp: temperature-sensor@49 {
+		#thermal-sensor-cells = <0>;
+		compatible = "nxp,pct2075";
+		reg = <0x49>;
+	};
+
+	temp_core: temperature-sensor@4c { /* temp. zynq die */
+		#thermal-sensor-cells = <1>;
+		compatible = "ti,tmp431";
+		reg = <0x4c>;
+	};
+
+	extrtc: rtc@51 {	/* realtime clock */
+		compatible = "epson,rx8571";
+		reg = <0x51>;
+	};
+};
+
+&qspi {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+	spi-max-frequency = <100000000>;
+	spi_flash: spiflash@0 {
+		u-boot,dm-pre-reloc;
+		compatible = "spidev", "spi-flash";
+		spi-max-frequency = <100000000>;
+		reg = <0>;
+	};
+};
+
+&i2c1 {
+	status = "okay";
+	clock-frequency = <100000>;
+};
+
+&sdhci0 {
+	status = "okay";
+	max-frequency = <25000000>;
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&usb0 {
+	status = "okay";
+	dr_mode = "host";
+	usb-phy = <&usb_phy0>;
+};
+
+&gpio0 {
+	u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/zynq-brsmarc2-vxworks.dtsi b/arch/arm/dts/zynq-brsmarc2-vxworks.dtsi
new file mode 100644
index 0000000..136fc52
--- /dev/null
+++ b/arch/arm/dts/zynq-brsmarc2-vxworks.dtsi
@@ -0,0 +1,143 @@ 
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * primary OS (vxWorks 6.9.4.x) specific parts for B&R BRSMARC2 boards
+ *
+ * Copyright (C) 2019 B&R Industrial Automation GmbH
+ */
+
+#include "zynq-brsmarc2-common.dtsi"
+
+/ {
+	fset: factory-settings {
+		compatible = "bur,fsetv1";
+		bl-version	= "                                ";
+		order-no	= "                                ";
+		cpu-order-no	= "                                ";
+		hw-revision	= "                                ";
+		serial-no	= <0>;
+		device-id	= <0x0>;
+		parent-id	= <0x0>;
+		hw-variant	= <0x0>;
+		hw-platform	= <0x0>;
+		fram-offset	= <0x0>;
+		fram-size	= <0x0>;
+		cache-disable	= <0x0>;
+		cpu-clock	= <0x0>;
+	};
+
+	aliases {
+		fset = &fset;
+	};
+
+	board {
+		status = "okay";
+		compatible = "bur,brsmarc2-som";
+		usb0mux-gpios = <&gpio0 68 GPIO_ACTIVE_HIGH>;
+		usb1mux-gpios = <&gpio0 69 GPIO_ACTIVE_HIGH>;
+		powerdown-gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
+		reset-gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
+	};
+
+	fpga: fpga@40000000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		status = "disabled";
+		compatible = "bur,zynqPL", "simple-bus";
+		reg = <0x40200000 0x1		/* version registers */
+		       0x40200004 0x1>;		/* misc registers */
+		bur,upddest = &spi_flash;
+		bur,updaddr = <0x100000>;
+		bur,updsize = <0x200000>;
+
+		plk: plk@80000000 {
+			status = "disabled";
+			compatible = "bur,DdVxIoEplSMP";
+			bur,hwtree = "IF9";
+			reg = <0x80000000 0x8000>;
+			interrupt-parent = <&intc>;
+			interrupts = <0 68 4>,
+				     <0 84 4>;
+			local-mac-address = [ 00 60 65 aa ab ac ];
+		};
+
+		x2x: x2x@40100000 {
+			status = "disabled";
+			compatible = "bur,xlk";
+			bur,hwtree = "IF10";
+			reg = <0x40100000 0x8000
+			       0x40108000 0x8000>;
+			interrupt-parent = <&intc>;
+			interrupts = <0 65 4>;
+		};
+
+		uart2: serial@40200800 {
+			status = "disabled";
+			compatible = "ns16550a", "bur,DdVxSf16x5xIO";
+			bur,hwtree = "IF8";
+			reg = <0x40200800 0x40>;
+			interrupt-parent = <&intc>;
+			interrupts = <0 66 4>;
+			term-gpios = <&gpio0 71 GPIO_ACTIVE_HIGH>;
+		};
+
+		uart3: serial@40200840 {
+			status = "disabled";
+			compatible = "ns16550a", "bur,DdVxSf16x5xIO";
+			bur,hwtree = "IF9";
+			reg = <0x40200840 0x40>;
+			interrupt-parent = <&intc>;
+			interrupts = <0 67 4>;
+			term-gpios = <&gpio0 71 GPIO_ACTIVE_HIGH>;
+		};
+
+		uart4: serial@40200900 {
+			status = "disabled";
+			compatible = "ns16550a", "bur,DdVxSf16x5xIO";
+			bur,hwtree = "IF20";
+			reg = <0x40200900 0x40>;
+			interrupt-parent = <&intc>;
+			interrupts = <0 88 4>;
+		};
+
+		uart5: serial@40200A00 {
+			status = "disabled";
+			compatible = "ns16550a", "bur,DdVxSf16x5xIO";
+			bur,hwtree = "IF21";
+			reg = <0x40200A00 0x40>;
+			interrupt-parent = <&intc>;
+			interrupts = <0 90 4>;
+		};
+	};
+};
+
+&i2c0 {
+	resetc: reset-controller@60 {
+		compatible = "bur,rststm";
+		reg = <0x60>;
+		hit-gpios = <&gpio0 84 GPIO_ACTIVE_HIGH>;
+		cooling-min-state = <0>;
+		cooling-max-state = <1>;	/* reset gets fired */
+		#cooling-cells = <2>;		/* min followed by max */
+	};
+};
+
+&can0 {
+	status = "disabled";
+	bur,hwtree = "IF6";
+	term-gpios = <&gpio0 70 GPIO_ACTIVE_HIGH>;
+};
+
+&can1 {
+	status = "disabled";
+	bur,hwtree = "IF7";
+	term-gpios = <&gpio0 71 GPIO_ACTIVE_HIGH>;
+};
+
+&ethernet_phy0 {
+		ti,ledcr = <0x0480>;
+		ti,rgmii-rxclk-shift;
+};
+
+&ethernet_phy1 {
+		ti,ledcr = <0x0480>;
+};
diff --git a/arch/arm/dts/zynq-brsmarc2.dts b/arch/arm/dts/zynq-brsmarc2.dts
new file mode 100644
index 0000000..b53a2e7
--- /dev/null
+++ b/arch/arm/dts/zynq-brsmarc2.dts
@@ -0,0 +1,8 @@ 
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * B&R BRSMARC2 board DTS file
+ *
+ * Copyright (C) 2019 B&R Industrial Automation GmbH
+ */
+
+#include "zynq-brsmarc2-vxworks.dtsi"
diff --git a/board/BuR/zynq/.gitignore b/board/BuR/zynq/.gitignore
new file mode 100644
index 0000000..fa64fbc
--- /dev/null
+++ b/board/BuR/zynq/.gitignore
@@ -0,0 +1 @@ 
+./ps7_init_gpl.c
diff --git a/board/BuR/zynq/MAINTAINERS b/board/BuR/zynq/MAINTAINERS
new file mode 100644
index 0000000..c6b3cfb
--- /dev/null
+++ b/board/BuR/zynq/MAINTAINERS
@@ -0,0 +1,6 @@ 
+BRSMARC2 BOARD
+M:	Hannes Schmelzer <hannes.schmelzer@br-automation.com>
+S:	Maintained
+F:	board/BuR/zynq/
+F:	include/configs/brsmarc2.h
+F:	configs/brsmarc2_defconfig
diff --git a/board/BuR/zynq/Makefile b/board/BuR/zynq/Makefile
new file mode 100644
index 0000000..85a4b77
--- /dev/null
+++ b/board/BuR/zynq/Makefile
@@ -0,0 +1,16 @@ 
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2019 Hannes Schmelzer <oe5hpm@oevsv.at> -
+# B&R Industrial Automation GmbH - http://www.br-automation.com
+#
+
+hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE) | sed -e 's/zynq-//')
+
+obj-y := ../common/common.o
+obj-y += ../common/br_resetc.o
+obj-y += $(hw-platform-y)/board.o
+
+obj-$(CONFIG_SPL_BUILD) += $(hw-platform-y)/ps7_init_gpl.o
+
+# Suppress "warning: function declaration isn't a prototype"
+CFLAGS_REMOVE_ps7_init_gpl.o := -Wstrict-prototypes
diff --git a/board/BuR/zynq/brsmarc2/board.c b/board/BuR/zynq/brsmarc2/board.c
new file mode 100644
index 0000000..0331087
--- /dev/null
+++ b/board/BuR/zynq/brsmarc2/board.c
@@ -0,0 +1,63 @@ 
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Board functions for B&R BRSMARC2 Board
+ *
+ * Copyright (C) 2019 Hannes Schmelzer <oe5hpm@oevsv.at>
+ * B&R Industrial Automation GmbH - http://www.br-automation.com
+ *
+ */
+#include <common.h>
+#include <fdtdec.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include "../../common/bur_common.h"
+#include "../../common/br_resetc.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_SPL_BUILD
+int board_init(void)
+{
+	/* reset pulse for peripherals */
+	gpio_request(9, "nRESET_PS_3V3");
+	gpio_direction_output(9, 1);
+
+	return 0;
+}
+#else
+int board_init(void)
+{
+	return 0;
+}
+#endif
+
+int board_late_init(void)
+{
+	int rc;
+	struct udevice *i2cdev;
+
+	br_resetc_bmode();
+	brdefaultip_setup(0, 0x57);
+
+	rc = i2c_get_chip_for_busnum(0, 0x5D, 1, &i2cdev);
+	if (rc >= 0)
+		rc = dm_i2c_write(i2cdev, 0xEF, NULL, 0);
+	if (rc != 0)
+		printf("WARN: cannot write to LEDs!\n");
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	if (fdtdec_setup_mem_size_base() != 0)
+		return -EINVAL;
+
+	/* simple test if ram_size determined from fdt is plausible */
+	gd->ram_size = get_ram_size((void *)gd->ram_base, gd->ram_size);
+
+	zynq_ddrc_init();
+
+	return 0;
+}
diff --git a/board/BuR/zynq/brsmarc2/ps7_init_gpl.c b/board/BuR/zynq/brsmarc2/ps7_init_gpl.c
new file mode 100644
index 0000000..d4e20d9
--- /dev/null
+++ b/board/BuR/zynq/brsmarc2/ps7_init_gpl.c
@@ -0,0 +1,276 @@ 
+// SPDX-License-Identifier: GPL-2.0+
+#include <asm/arch/ps7_init_gpl.h>
+
+unsigned long ps7_pll_init_data_3_0[] = {
+	EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x000FA220U),
+	EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x00028000U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
+	EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x0012C220U),
+	EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00020000U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
+	EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001452C0U),
+	EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x0001E000U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
+	EMIT_WRITE(0XF8000004, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+unsigned long ps7_clock_init_data_3_0[] = {
+	EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00700F01U),
+	EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U),
+	EMIT_MASKWRITE(0XF800013C, 0x00000011U, 0x00000011U),
+	EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00500801U),
+	EMIT_MASKWRITE(0XF8000144, 0x03F03F71U, 0x00500141U),
+	EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00000A01U),
+	EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A01U),
+	EMIT_MASKWRITE(0XF8000158, 0x00003F33U, 0x00000503U),
+	EMIT_MASKWRITE(0XF800015C, 0x03F03F33U, 0x00501903U),
+	EMIT_MASKWRITE(0XF8000160, 0x007F007FU, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U),
+	EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00400500U),
+	EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01DFC4CDU),
+	EMIT_WRITE(0XF8000004, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+unsigned long ps7_ddr_init_data_3_0[] = {
+	EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU, 0x00001040U),
+	EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
+	EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
+	EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
+	EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004159AU),
+	EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44D258D4U),
+	EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0xB2024127U),
+	EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU, 0x2B08B290U),
+	EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
+	EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000018U),
+	EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040970U),
+	EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x000116D4U),
+	EMIT_MASKWRITE(0XF8006038, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U),
+	EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+	EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0FF66666U),
+	EMIT_MASKWRITE(0XF8006048, 0x0003F03FU, 0x0003C008U),
+	EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
+	EMIT_MASKWRITE(0XF8006058, 0x00010000U, 0x00000000U),
+	EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
+	EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
+	EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
+	EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284545U),
+	EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
+	EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U),
+	EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U),
+	EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
+	EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+	EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
+	EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+	EMIT_MASKWRITE(0XF80060B4, 0x00000200U, 0x00000200U),
+	EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x0020006AU),
+	EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
+	EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x0001D400U),
+	EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x0001C400U),
+	EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x0001BC00U),
+	EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x0001C800U),
+	EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x0000007AU),
+	EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007DU),
+	EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x0000007EU),
+	EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000CAU),
+	EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000C6U),
+	EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000C4U),
+	EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000C7U),
+	EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000BAU),
+	EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BDU),
+	EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000C0U),
+	EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000BEU),
+	EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU, 0x00040080U),
+	EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FD04U),
+	EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF8006208, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF800620C, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006210, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006214, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U, 0x00000000U),
+	EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
+	EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A8U),
+	EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+	EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U),
+	EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+	EMIT_EXIT(),
+};
+
+unsigned long ps7_mio_init_data_3_0[] = {
+	EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C068U),
+	EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F98068U),
+	EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F98068U),
+	EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F98068U),
+	EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000260U),
+	EMIT_MASKWRITE(0XF8000B70, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
+	EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU, 0x00000823U),
+	EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00000700U),
+	EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000700U),
+	EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U),
+	EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00000700U),
+	EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x000007A0U),
+	EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x000007A0U),
+	EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x000007A0U),
+	EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x000007A0U),
+	EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x000016E1U),
+	EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x000006E0U),
+	EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00000302U),
+	EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00000302U),
+	EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00000302U),
+	EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00000302U),
+	EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00000302U),
+	EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00000302U),
+	EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000303U),
+	EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000303U),
+	EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000303U),
+	EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000303U),
+	EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000303U),
+	EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000303U),
+	EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000204U),
+	EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000205U),
+	EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000204U),
+	EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000205U),
+	EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000204U),
+	EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000204U),
+	EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000204U),
+	EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000204U),
+	EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000205U),
+	EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000204U),
+	EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000204U),
+	EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000204U),
+	EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U),
+	EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00000321U),
+	EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU, 0x00000320U),
+	EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x00000320U),
+	EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x00000321U),
+	EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x00000340U),
+	EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x00000340U),
+	EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000280U),
+	EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000280U),
+	EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x00380037U),
+	EMIT_WRITE(0XF8000004, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+unsigned long ps7_peripherals_init_data_3_0[] = {
+	EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
+	EMIT_WRITE(0XF8000004, 0x0000767BU),
+	EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U),
+	EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU),
+	EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U),
+	EMIT_MASKWRITE(0XE0000004, 0x000003FFU, 0x00000020U),
+	EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
+	EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_EXIT(),
+};
+
+unsigned long ps7_post_config_3_0[] = {
+	EMIT_WRITE(0XF8000008, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
+	EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_WRITE(0XF8000004, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+int ps7_post_config(void)
+{
+	return ps7_config(ps7_post_config_3_0);
+}
+
+int ps7_init(void)
+{
+	int ret;
+
+	ret = ps7_config(ps7_mio_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_pll_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_clock_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_ddr_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	ret = ps7_config(ps7_peripherals_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	return PS7_INIT_SUCCESS;
+}
diff --git a/board/BuR/zynq/config.mk b/board/BuR/zynq/config.mk
new file mode 100644
index 0000000..17e3d57
--- /dev/null
+++ b/board/BuR/zynq/config.mk
@@ -0,0 +1,49 @@ 
+# SPDX-License-Identifier:	GPL-2.0+
+#
+# Copyright (C) 2019 Hannes Schmelzer <oe5hpm@oevsv.at> -
+# B&R Industrial Automation GmbH - http://www.br-automation.com
+#
+
+hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE) | sed -e 's/zynq-//')
+
+payload_off :=$(shell printf "%d" $(CONFIG_SYS_SPI_U_BOOT_OFFS))
+
+fpga_path := $(shell echo $(KBUILD_SRC)/board/$(BOARDDIR)/$(hw-platform-y))
+fpga_src  := $(shell ls $(fpga_path)/*.bit 2>/dev/null)
+fpga_file := $(shell echo $(fpga_src) | rev | cut -d/ -f1 | rev)
+fpga_off  := $(shell printf "%d" \
+	     $(shell cat $(fpga_path)/${fpga_file}.offset 2>/dev/null))
+flen_min  := $(shell expr ${payload_off} + ${fpga_off})
+
+quiet_cmd_prodbin = PRODBIN $@ $(payload_off)
+cmd_prodbin = \
+	dd if=/dev/zero bs=1 count=${flen_min} 2>/dev/null | tr "\000" "\377" >$@ && \
+	dd conv=notrunc bs=1 if=spl/boot.bin of=$@ seek=0 2>/dev/null && \
+	test -z ${fpga_src} && dd conv=notrunc bs=1 if=u-boot-dtb.img of=$@ seek=$(payload_off) 2>/dev/null && \
+	test -z ${fpga_src} || ( \
+		dd conv=notrunc bs=1 if=u-boot-dtb.img of=$@ seek=$(payload_off) 2>/dev/null; \
+		dd obs=1 if=$(fpga_file) of=$@ seek=$(fpga_off) 2>/dev/null \
+		)
+
+quiet_cmd_prodzip = SAPZIP  $@
+cmd_prodzip =					\
+	test -d misc && rm -r misc;		\
+	mkdir misc &&				\
+	cp spl/boot.bin misc/ &&		\
+	cp u-boot-dtb.img misc/ &&		\
+	zip -9 -r $@ misc/* >/dev/null $<
+
+quiet_cmd_fpga = FPGA    $@ ($(fpga_file)) @ $(fpga_off)
+cmd_fpga = test -z ${fpga_src} || cp ${fpga_src} $(fpga_file)
+
+$(hw-platform-y)_fpga:
+	$(call if_changed,fpga)
+
+$(hw-platform-y)_prog.bin: u-boot-dtb.img spl/boot.bin $(hw-platform-y)_fpga
+	$(call if_changed,prodbin)
+
+$(hw-platform-y)_prod.zip: $(hw-platform-y)_prog.bin
+	$(call if_changed,prodzip)
+
+
+ALL-y += $(hw-platform-y)_prod.zip
diff --git a/configs/brsmarc2_defconfig b/configs/brsmarc2_defconfig
new file mode 100644
index 0000000..b325eeb
--- /dev/null
+++ b/configs/brsmarc2_defconfig
@@ -0,0 +1,75 @@ 
+CONFIG_ARM=y
+CONFIG_SYS_VENDOR="BuR"
+CONFIG_SYS_CONFIG_NAME="brsmarc2"
+CONFIG_ARCH_ZYNQ=y
+CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_SPL_GPIO_SUPPORT=y
+# CONFIG_SPL_MMC_SUPPORT is not set
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0x20000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL=y
+CONFIG_ZYNQ_SDHCI_MAX_FREQ=100000000
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=0
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run b_default"
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_SPL_RAM_SUPPORT is not set
+CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_BOOTD is not set
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_FPGA_LOADFS=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+# CONFIG_CMD_MISC is not set
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_DEFAULT_DEVICE_TREE="zynq-brsmarc2"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQPL=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_CADENCE=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_SPI_FLASH=y
+CONFIG_SF_DEFAULT_SPEED=30000000
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_MII=y
+CONFIG_ZYNQ_GEM=y
+CONFIG_ZYNQ_SERIAL=y
+CONFIG_ZYNQ_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_STORAGE=y
+# CONFIG_EFI_LOADER is not set
diff --git a/include/configs/brsmarc2.h b/include/configs/brsmarc2.h
new file mode 100644
index 0000000..0b37fcc
--- /dev/null
+++ b/include/configs/brsmarc2.h
@@ -0,0 +1,150 @@ 
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * specific parts for B&R brsmarc2 SoM
+ *
+ * Copyright (C) 2019 Hannes Schmelzer <oe5hpm@oevsv.at> -
+ * B&R Industrial Automation GmbH - http://www.br-automation.com
+ *
+ */
+
+#ifndef __CONFIG_BRSMARC2_H__
+#define __CONFIG_BRSMARC2_H__
+
+#include <configs/bur_cfg_common.h>
+
+/* Cache options */
+#define CONFIG_SYS_L2CACHE_OFF
+#ifndef CONFIG_SYS_L2CACHE_OFF
+# define CONFIG_SYS_L2_PL310
+# define CONFIG_SYS_PL310_BASE		0xf8f02000
+#endif
+
+#define ZYNQ_SCUTIMER_BASEADDR		0xF8F00600
+#define CONFIG_SYS_TIMERBASE		ZYNQ_SCUTIMER_BASEADDR
+#define CONFIG_SYS_TIMER_COUNTS_DOWN
+#define CONFIG_SYS_TIMER_COUNTER	(CONFIG_SYS_TIMERBASE + 0x4)
+
+/* Serial drivers */
+#define CONFIG_BAUDRATE		115200
+/* The following table includes the supported baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
+
+/* MMC */
+#define CONFIG_ZYNQ_HISPD_BROKEN
+
+/* USB */
+#define CONFIG_EHCI_IS_TDI
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	1
+
+/* Environment */
+#define CONFIG_SYS_AUTOLOAD	"no"
+
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#define CONFIG_ENV_OFFSET_REDUND		(CONFIG_ENV_OFFSET + \
+						 CONFIG_ENV_SECT_SIZE)
+#define CONFIG_EXTRA_ENV_SETTINGS	\
+BUR_COMMON_ENV \
+"board_id=0xFF\0" \
+"scradr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+"dtbaddr=0x4000000\0" \
+"loadaddr=0x2000000\0" \
+"fpgaaddr=fdt get value fpgabase /fpga bur,updaddr;" \
+" fdt get value fpgasize /fpga bur,updsize\0" \
+"fpga=setenv fpgastatus disabled; run fpgaaddr;" \
+" sf read ${loadaddr} ${fpgabase} ${fpgasize} &&" \
+" fpga loadb 0 ${loadaddr} ${fpgasize} && setenv fpgastatus okay\0" \
+"fpgastatus=disabled\0" \
+"fpgaupd=run fpgaaddr && tftp ${loadaddr} X20CP04xx.bit &&" \
+" sf erase ${fpgabase} +${filesize} &&" \
+" sf write ${loadaddr} ${fpgabase} ${filesize}\0" \
+"netupd=tftp ${loadaddr} boot.bin && sf probe &&" \
+" sf erase 0 +${filesize} && sf write ${loadaddr} 0 ${filesize} &&" \
+" tftp ${loadaddr} u-boot-dtb.img &&" \
+" sf erase 0x40000 +${filesize} && sf write ${loadaddr} 0x40000 ${filesize}\0" \
+"cfgscr=mw ${dtbaddr} 0;" \
+" sf probe && sf read ${scradr} 0xC0000 0x10000 && source ${scradr};" \
+" fdt addr ${dtbaddr} || cp ${fdtcontroladdr} ${dtbaddr} 4000\0" \
+"vxargs=setenv bootargs gem(0,0)host:vxWorks h=${serverip}" \
+" e=${ipaddr}:${netmask} g=${gatewayip} u=vxWorksFTP pw=vxWorks\0" \
+"vxfdt=fdt addr ${dtbaddr}; fdt resize 0x10000;" \
+" fdt set /fpga status ${fpgastatus};" \
+" fdt boardsetup\0" \
+"startvx=run vxargs && mw 0x1100 0 && run vxfdt &&" \
+" bootm ${loadaddr} - ${dtbaddr}\0" \
+"b_break=0\0" \
+"b_tgts_std=mmc spi usb0 net0 net1\0" \
+"b_tgts_rcy=spi usb0 net0 net1\0" \
+"b_tgts_pme=usb0 net0 net1 mmc spi\0" \
+"b_deftgts=if test ${b_mode} = 12; then setenv b_tgts ${b_tgts_pme};" \
+" elif test ${b_mode} = 0; then setenv b_tgts ${b_tgts_rcy};" \
+" else setenv b_tgts ${b_tgts_std}; fi\0" \
+"b_mmc=run fpga; mmc dev 0; load mmc 0 ${loadaddr} arimg && run startvx\0" \
+"b_spi=run fpga; sf read ${loadaddr} 900000 700000 && run startvx\0" \
+"b_net0=tftp ${scradr} netscr-brsmarc2-${board_id}.img && source ${scradr}\0" \
+"b_net1=tftp ${scradr} netscript.img && source ${scradr}\0" \
+"b_usb0=usb start && load usb 0 ${scradr} bootscr.img && source ${scradr}\0" \
+"b_default=run b_deftgts; for target in ${b_tgts};"\
+" do run b_${target}; if test ${b_break} = 1; then; exit; fi; done\0"
+
+#define CONFIG_SYS_LOAD_ADDR		0xC0000	/*
+						 * default load and execution
+						 * address for loads / scripts
+						 */
+/* Support both device trees and ATAGs. */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_MACH_TYPE		0xFFFFFFFF
+
+/* Miscellaneous configurable options */
+#define CONFIG_CLOCKS
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+#define CONFIG_SYS_BOOTM_LEN		(32 * 1024 * 1024)
+/* Physical Memory map */
+#define CONFIG_SYS_TEXT_BASE		0x4000000
+
+#define CONFIG_SYS_SDRAM_BASE		0
+
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x1000)
+
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_MALLOC_LEN
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+					CONFIG_SYS_INIT_RAM_SIZE - \
+					GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_SPI_U_BOOT_OFFS	0x40000
+/* SPL part */
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_I2C_SUPPORT
+
+/* Disable dcache for SPL just for sure */
+#define CONFIG_SYS_DCACHE_OFF
+
+#ifdef CONFIG_ZYNQ_QSPI
+# define CONFIG_SPL_SPI_LOAD
+#endif /* CONFIG_ZYNQ_QSPI */
+
+/* SP location before relocation, must use scratch RAM */
+#define CONFIG_SPL_TEXT_BASE		0x0
+/* 3 * 64kB blocks of OCM - one is on the top because of bootrom */
+#define CONFIG_SPL_MAX_SIZE		0x30000
+/* The highest 64k OCM address */
+#define OCM_HIGH_ADDR			0xffff0000
+/* Just define any reasonable size */
+#define CONFIG_SPL_STACK_SIZE		0x2000
+/* SPL stack position - and stack goes down */
+#define CONFIG_SPL_STACK		(OCM_HIGH_ADDR + CONFIG_SPL_STACK_SIZE)
+/* On the top of OCM space */
+#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SPL_STACK + \
+					 GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x8000
+/* BSS setup */
+#define CONFIG_SPL_BSS_START_ADDR	0x100000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x100000
+#define CONFIG_SYS_UBOOT_START		CONFIG_SYS_TEXT_BASE
+#endif /* CONFIG_SPL_BUILD */
+#endif /* __CONFIG_BRSMARC2_H__ */