From patchwork Tue Jul 16 16:42:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1132871 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="M8It/1Mu"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 45p5sF5HGfz9sNC for ; Wed, 17 Jul 2019 02:46:57 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 764B9C21EC2; Tue, 16 Jul 2019 16:45:27 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=FREEMAIL_FROM, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 4B62DC21F07; Tue, 16 Jul 2019 16:43:55 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id EEB75C21EC8; Tue, 16 Jul 2019 16:43:16 +0000 (UTC) Received: from mail-pl1-f177.google.com (mail-pl1-f177.google.com [209.85.214.177]) by lists.denx.de (Postfix) with ESMTPS id C7EB3C21E68 for ; Tue, 16 Jul 2019 16:43:12 +0000 (UTC) Received: by mail-pl1-f177.google.com with SMTP id a93so10386904pla.7 for ; Tue, 16 Jul 2019 09:43:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=SLBHPpqA5F2ySCxyQ7F8qnRU8cs1bnAL+citE4MP7+w=; b=M8It/1Mu/qhUSmIyki+fHrs70h2VTzt7pkMEdLmsosEXIuWiXzmstuVI74UaQn0ihV O9P6IfN2+q5mfAxaf9oAyPQEzKdafSFqFfHSVFvsPSdUHouKSL7CMsKqNc1RHQIcmwEl UB2Xrc9eeYXE458ORWxl5gvIEkRT+M99riwJpTMQsalOdewkYgtvomguq0lYK+trrqRP tIqsOeBSiYzXPFeGwxu0fYjX+/3umFBDFEYP0xlbrRAE85QVE3gPiN3IcQp0VzxMIvJN qWopP8otE3hBKzdbedVouZlQEdQfyVj0VNBppBlDXxrWAqz/5v10rw4LLNGyeFPsIUFg cKQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=SLBHPpqA5F2ySCxyQ7F8qnRU8cs1bnAL+citE4MP7+w=; b=rf3r1PuHfeeiTXYMA0xf42hKzFSmIKF2CoXiQc0m79JTuW26BQ1GX+1/GTK95JGNRq QnejgHYPjxv+QDAYQ4LBP1Lj0OcdxyHoOHq/o7uAqyhxXsi6Yy+rrY9qkA/z50Foy77Y cqC/81dcLcyXWvUyaXPCm8kaitfZutsRfWX+LM1c6IYz5xKdtWEwP1BC+aVD66c62FT3 IBXCSL2zVxUWYf0+EE8TxQyHArfkeQT2HAp7JaS/5OS6cArxbdy5YOovbPnEu+WmE984 IRU9zHkusuIwtX3UAnORubbl/8u5rxc/AHZ7iE/WE+TBmDtUGweZfH+EtgTdXnltWHN9 POKA== X-Gm-Message-State: APjAAAXpl5rKBuSKBqXwTEfBcAz6xfVVOjh+FABtWPfnNqEahLN+e1iF gc2+qO5WICXwe+SZ6I1tYOM= X-Google-Smtp-Source: APXvYqxP50aAnxcWuQ6U2TsAzN3d3ezkVL1QyslDTyfF0vmOq2SGZf0Te+IISwWeNEwZ4HxqMS5NJA== X-Received: by 2002:a17:902:54d:: with SMTP id 71mr36149732plf.140.1563295390721; Tue, 16 Jul 2019 09:43:10 -0700 (PDT) Received: from localhost.localdomain (unknown-224-80.windriver.com. [147.11.224.80]) by smtp.gmail.com with ESMTPSA id h12sm26017441pje.12.2019.07.16.09.43.09 (version=TLS1 cipher=AES128-SHA bits=128/128); Tue, 16 Jul 2019 09:43:10 -0700 (PDT) From: Bin Meng To: Tom Rini , Simon Glass , Wolfgang Denk , Heinrich Schuchardt , Mario Six , U-Boot Mailing List Date: Tue, 16 Jul 2019 09:42:54 -0700 Message-Id: <1563295374-1504-10-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1563295374-1504-1-git-send-email-bmeng.cn@gmail.com> References: <1563295374-1504-1-git-send-email-bmeng.cn@gmail.com> Subject: [U-Boot] [RFC PATCH 9/9] doc: board: Add Intel Crown Bay board doc X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This extracts Intel Crown Bay board specific information from README.x86, converts plain text documentation to reST format and adds it to Sphinx TOC tree. No essential content change. Signed-off-by: Bin Meng --- doc/README.x86 | 37 --------------------------------- doc/board/index.rst | 2 ++ doc/board/intel/crownbay.rst | 49 ++++++++++++++++++++++++++++++++++++++++++++ doc/board/intel/index.rst | 4 ++++ 4 files changed, 55 insertions(+), 37 deletions(-) create mode 100644 doc/board/intel/crownbay.rst create mode 100644 doc/board/intel/index.rst diff --git a/doc/README.x86 b/doc/README.x86 index 8e0a3f3..8077ff3 100644 --- a/doc/README.x86 +++ b/doc/README.x86 @@ -203,43 +203,6 @@ Flash map for samus / broadwell: --- -Intel Crown Bay specific instructions for bare mode: - -U-Boot support of Intel Crown Bay board [4] relies on a binary blob called -Firmware Support Package [5] to perform all the necessary initialization steps -as documented in the BIOS Writer Guide, including initialization of the CPU, -memory controller, chipset and certain bus interfaces. - -Download the Intel FSP for Atom E6xx series and Platform Controller Hub EG20T, -install it on your host and locate the FSP binary blob. Note this platform -also requires a Chipset Micro Code (CMC) state machine binary to be present in -the SPI flash where u-boot.rom resides, and this CMC binary blob can be found -in this FSP package too. - -* ./FSP/QUEENSBAY_FSP_GOLD_001_20-DECEMBER-2013.fd -* ./Microcode/C0_22211.BIN - -Rename the first one to fsp.bin and second one to cmc.bin and put them in the -board directory. - -Note the FSP release version 001 has a bug which could cause random endless -loop during the FspInit call. This bug was published by Intel although Intel -did not describe any details. We need manually apply the patch to the FSP -binary using any hex editor (eg: bvi). Go to the offset 0x1fcd8 of the FSP -binary, change the following five bytes values from orginally E8 42 FF FF FF -to B8 00 80 0B 00. - -As for the video ROM, you need manually extract it from the Intel provided -BIOS for Crown Bay here [6], using the AMI MMTool [7]. Check PCI option ROM -ID 8086:4108, extract and save it as vga.bin in the board directory. - -Now you can build U-Boot and obtain u-boot.rom - -$ make crownbay_defconfig -$ make all - ---- - Intel Cougar Canyon 2 specific instructions for bare mode: This uses Intel FSP for 3rd generation Intel Core and Intel Celeron processors diff --git a/doc/board/index.rst b/doc/board/index.rst index 4a65def..34e59de 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -4,3 +4,5 @@ Board-specific doc .. toctree:: :maxdepth: 2 + + intel/index diff --git a/doc/board/intel/crownbay.rst b/doc/board/intel/crownbay.rst new file mode 100644 index 0000000..d77cece --- /dev/null +++ b/doc/board/intel/crownbay.rst @@ -0,0 +1,49 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +:author: Bin Meng + +.. toctree:: + :maxdepth: 2 + +Intel CrownBay CRB +================== + +U-Boot support of Intel Crown Bay board `[1]`_ relies on a binary blob called +Firmware Support Package `[2]`_ to perform all the necessary initialization +steps as documented in the BIOS Writer Guide, including initialization of the +CPU, memory controller, chipset and certain bus interfaces. + +Download the Intel FSP for Atom E6xx series and Platform Controller Hub EG20T, +install it on your host and locate the FSP binary blob. Note this platform +also requires a Chipset Micro Code (CMC) state machine binary to be present in +the SPI flash where u-boot.rom resides, and this CMC binary blob can be found +in this FSP package too. + +* ./FSP/QUEENSBAY_FSP_GOLD_001_20-DECEMBER-2013.fd +* ./Microcode/C0_22211.BIN + +Rename the first one to fsp.bin and second one to cmc.bin and put them in the +board directory. + +Note the FSP release version 001 has a bug which could cause random endless +loop during the FspInit call. This bug was published by Intel although Intel +did not describe any details. We need manually apply the patch to the FSP +binary using any hex editor (eg: bvi). Go to the offset 0x1fcd8 of the FSP +binary, change the following five bytes values from orginally E8 42 FF FF FF +to B8 00 80 0B 00. + +As for the video ROM, you need manually extract it from the Intel provided +BIOS for Crown Bay here `[3]`_, using the AMI MMTool `[4]`_. Check PCI option +ROM ID 8086:4108, extract and save it as vga.bin in the board directory. + +Now you can build U-Boot and obtain u-boot.rom + +.. code-block:: shell + + $ make crownbay_defconfig + $ make all + +.. _[1]: http://www.intel.com/content/www/us/en/embedded/design-tools/evaluation-platforms/atom-e660-eg20t-development-kit.html +.. _[2]: http://www.intel.com/fsp +.. _[3]: http://www.intel.com/content/www/us/en/secure/intelligent-systems/privileged/e6xx-35-b1-cmc22211.html +.. _[4]: http://www.ami.com/products/bios-uefi-tools-and-utilities/bios-uefi-utilities/ diff --git a/doc/board/intel/index.rst b/doc/board/intel/index.rst new file mode 100644 index 0000000..0e5eb47 --- /dev/null +++ b/doc/board/intel/index.rst @@ -0,0 +1,4 @@ +.. toctree:: + :maxdepth: 2 + + crownbay \ No newline at end of file